Chapter 3 Hardware Overview
VXI-MIO Series User Manual 3-16
National Instruments Corporation
This figure shows that CONVERT* can be generated from a number of
sources, including the external signals VXI TTL Trig<0..4>,
VXI ECL Trig<0..1>, and PFI<0..9>, and the internal signals Sample
Interval Counter TC and GPCTR0_OUT.
Many of these timing signals are also available as outputs on the
VXIbus trigger, as indicated in the VXIbus Triggers section later in this
chapter, and on the PFI pins, as indicated in Chapter 4, Signal
Connections.
Programmable Function Inputs
The 10 PFIs are connected to the signal routing multiplexer for each
timing signal, and software can select one of the PFIs as the external
source for a given timing signal. It is important to note that any of the
PFIs can be used as an input by any of the timing signals and that
multiple timing signals can use the same PFI simultaneously. This
flexible routing scheme reduces the need to change physical
connections to the I/O connector for different applications.
You can also individually enable each of the PFI pins to output a
specific internal timing signal. For example, if you need the UPDATE*
signal as an output on the I/O connector, your software can turn on the
output driver for the PFI5/UPDATE* pin.
Module and Timebase
Many functions that the VXI-MIO Series modules perform require a
frequency timebase to generate the necessary timing signals for
controlling A/D conversions, DAC updates, or general-purpose signals
at the I/O connector.
A VXI-MIO Series module can use either its internal 20 MHz timebase,
which is phase-locked to CLK10 on the VXIbus, or a timebase received
over a VXIbus trigger line. In addition, if you configure the module to
use the internal timebase, you can also program the module to drive its
internal timebase over the VXIbus trigger line to another module that is
programmed to receive this timebase signal. This clock source, whether
local or from the VXIbus trigger line, is used directly by the module as
the primary frequency source. The default configuration at startup is to
use the internal timebase without driving the VXIbus trigger line
timebase signal. This timebase is software-selectable.