NEC PH133 manual CPU Module

memory module. The two modules provide up to 768 MB of high-speed memory.

Each module has three memory banks. Each bank consists of four SIMM sockets. Each socket can hold an 8, 16, or 32 MB approved fast-page parity SIMM. You can install any size SIMM in any bank but all four SIMMs in a bank must be the same size. SIMM height must not exceed one inch; taller SIMMs will interfere with an adjacent CPU module or ECC memory module.

The ECC memory module detects and corrects single-bit errors from DRAM (Dynamic Random Access Memory) in real time, allowing your system to function normally. It detects all double-bit errors but does not correct them. It also detects all three-bit and four-bit adjacent errors in a DRAM nibble but does not correct them. When one of these multiple-bit errors occurs, the ECC memory module generates an NMI (NonMaskable Interrupt) and usually halts the system. The data transfer width of the ECC memory module is 64/128 bits. It is compatible with all Pentium processor modules.

The server supports both base (conventional) and extended memory. Base memory is located at addresses 00000H to 9FFFFH (the first 640 KB). Extended memory begins at address 100000H (1 M) and extends to the limit of addressable memory (4 G).

Some operating systems and application programs use base memory (for example, MS-DOS, OS/2, and UNIX). Other operating systems use both conventional and extended memory (for example, OS/2 and UNIX).

MS-DOS does not use extended memory. However, some MS-DOS utility programs such as RAM disks, disk caches, print spoolers, and windowing environments use extended memory for better performance.

CPU Module

The server system board accepts one or two CPU modules, each capable of supporting one or two Pentium processors. Depending on system configuration, the module(s) contain single or dual Pentium processors and a memory bus controller (see Table 1-1 for system CPU module configurations).

The dual processor module provides a symmetric multiprocessing (SMP) environment. In SMP, all processors are equal and have no preassigned tasks. Distributing the processing loads between both processors increases system performance. This is particularly useful when application demand is low and the I/O request load is high. In the SMP environment, both processors share a common bus, the same interrupt structure, and access to common memory and I/O channels. The SMP implementation conforms to MP Specification Version 1.4.

The CPU modules are compatible with all 32-bit software written for the Intel386Ô , Intel486Ô , and Intel Pentium processors. Operating system support includes Novell NetWare, MS-DOS, and Windows NT.

The single Pentium processor module uses the Intel 82497 cache controller and Intel 82492 SRAM components to provide 512 KB of zero wait state two-way associative cache.

The dual Pentium processor module uses the Intel 82498 cache controller and Intel 82493 SRAM components to provide 1 MB of zero wait state two-way associative