CHAPTER 4 CAUTIONS
Users Manual U15447EJ1V0UM 25
4.2 NMI Signal
The input signal (NMI signal) from the target system is delayed (tpD = 0.25 ns (TYP.)) because it passes through
QS3125 (Q switch), and I/O signals (ports 4, 5, 6, 9, 11) pass through QS3384 (Q switch) before it is input to the
emulator chip.
In addition, the DC characteristics change. The input voltage becomes VIH = 2.0 V (MIN.), VIL = 0.8 V (MAX.), and
the input current becomes IIN = ±0.5
µ
A (MAX.).
Figure 4-2. NMI Signal Flow Path
4.3 VPP Signal
The VPP signal from the target system is left open in the emulator.
4.4 NMI Signal Mask Function
When using the P00/NMI pin in the port mode, do not mask the NMI signal.
NMI pin QS3125
IE-703079-MC-EM1
Port pin QS3125
Target
system Emulator chip
NMI signal
Port signal