CBT3126_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 23 October 2008 7 of 15
NXP Semiconductors CBT3126
Quad FET bus switch
12. Test information

Test data is given inTable9.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 7. Test circuit for measuring switching times

VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aae331
VEXT
VCC
VIVO
DUT
CL
RT
RL
RL
G

Table 9. Test data

Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH

4.5 V to 5.5 V GND to 3.0 V ≤ 2.5 ns 50 pF 500 Ωopen 7.0 V open