NXP Semiconductors SA58670A 11. Application information

SA58670A_2 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 02 — 23 October 2008 16 of 24

NXP Semiconductors SA58670A

2.1 W/channel stereo class-D audio ampliﬁer

11. Application information

11.1 Power supply decoupling considerations

The SA58670A is a stereo class-D audio ampliﬁer that requires proper supply voltage

decouplingto ensure the rated performance for THD+N and power efﬁciency. Todecouple

high frequency transients, supply voltage spikes and digital noise on the supply voltage

busline, a low Equivalent Series Resistance (ESR) capacitor of typically 1 µF is placed as

close as possible to the PVDD pins of the SA58670A. It is important to place the

decoupling capacitor at the supply voltagepins of the SA58670A because any resistance

or inductance in the PCB trace between the SA58670A and the capacitor can cause a

lossin efﬁciency. Additional decoupling using a larger capacitor, 4.7 µF or greater, may be

done on the supply voltageconnection on the PCB to ﬁlter low frequency signals. Usually

this is not required due to high PSRR of the SA58670A.

11.2 Input capacitor selection

The SA58670A does not require input coupling capacitors when used with a differential

audiosource that is biased from 0.5 Vto VDD −0.8 V. In other words, the input signal must

be biased within the common-mode input voltage (Vi(cm)) range. If high-pass ﬁltering is

required or if it is driven using a single-ended source, input coupling capacitors are

required.

The 3 dB cut-off frequency created by the input coupling capacitor and the input resistors

(see Table6) is calculated by Equation1:

(1)

Fig 16. SA58670A application schematic

002aad665

SA58670A

OUTRP

OUTRN

10 µF

1 nF

1 nF

FB

FB

1 nF

1 nF

OUTLP

OUTLN

VDD

G1

VDD

PVDD

PGND

1 µF

VDD

10 µF

1 µF

VDD

SDL SDR AVDD

10 µF1 µF

PGND

VDD

PVDD

G0

INLP

1 µF

INLN

1 µF

differential inputs

left channel

INRN

1 µF

INRP

1 µF

differential inputs

right channel

AGND

FB

FB

f3dB–1

2πRi

×Ci

×

------------------------------

=

Contents

Main 1. General description 2. Features 3. Applications SA58670A Rev. 02 23 October 2008 Product data sheet 2.1 W/channel stereo class-D audio amplier Product data sheet Rev. 02 23 October 2008 2 of 24 2.1 W/channel stereo class-D audio amplier nEducational toy 4. Ordering information Fig 1. Block diagram 5. Block diagram Refer toTable 6 for gain selection. SA58670A 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). NXP Semiconductors SA58670A 8. Static characteristics C; unless otherwise specied =25 T . 9. Dynamic characteristics ; unless otherwise specied =8 =25 T 10. Typical performance curves Fig 3. Total harmonic distortion-plus-noise as a function of output power; RL=8 a. Gv(cl) =24dB b. Gv(cl) = 6 dB. fi=1 kHz. (1) VDD= 2.5 V. (2) VDD= 3.6 V. (3) VDD= 5.0 V. NXP Semiconductors SA58670A a. Gv(cl) =24dB. Fig 4. Total harmonic distortion-plus-noise as a function of output power; RL=4 b. Gv(cl) = 6 dB. fi=1 kHz. (1) VDD= 2.5 V. (2) VDD= 3.6 V. (3) VDD= 5.0 V. Fig 5. Total harmonic distortion-plus-noise as a function of frequency; VDD= 2.5 V Fig 6. Total harmonic distortion-plus-noise as a function of frequency; VDD= 3.6 V Fig 7. Total harmonic distortion-plus-noise as a function of frequency; VDD= 5.0 V Fig 8. Crosstalk (stepped all-to-one) as a function of frequency (1) Left channel. (2) Right channel. Fig 9. Noise output voltage (RMS value) as a function of frequency (1) VDD = 2.5 V. Fig 10. Crosstalk (one-to-one) as a function of frequency (3) VDD = 5.0 V. (1) left channel; RL=8. (2) right channel; RL=4. (3) right channel; RL=8. (1) VDD = 2.5 V. Fig 13. Supply current as a function of output power (3) VDD = 5.0 V. (1) VDD = 5.0 V. Fig 14. Power dissipation as a function of output power (3) VDD = 2.5 V. Fig 15. Output power efciency as a function of output power (1) VDD = 5.0 V. (3) VDD = 2.5 V. 11. Application information 11.1 Power supply decoupling considerations 11.2 Input capacitor selection 11.3 PCB layout considerations 11.4 Filter-free operation and ferrite bead lters 11.5 Efciency and thermal considerations 12. Test information 11.6 Additional thermal information 13. Package outline SOT917-1 Fig 18. Package outline SOT917-1 (HVQFN20) 14. Soldering of SMD packages 14.4 Reow soldering For further information on temperature proles, refer to Application Note AN10365 Surface mount reow soldering description . 15. Abbreviations 16. Revision history Product data sheet Rev. 02 23 October 2008 23 of 24 17. Legal information 17.1 Data sheet status 17.2 Denitions 17.3 Disclaimers 17.4 Trademarks 19. Contents