Counter Input Modes 5 Debounce Module …… 5-1
Terms Applicable to Counter Modes…….5-5
Counter Options …… 5-5
Counter/Totalize Mode …… 5-6
Period Mode …… 5-8
Pulsewidth Mode …… 5-11
Timing Mode …… 5-13
Encoder Mode …… 5-15
Each of the high-speed, 32-bit counter channels can be configured for counter, period, pulse width, time
between edges, or encoder modes.
Debounce
Each channel’s output can be debounced with 16 programmable debounce times from 500 ns to 25.5 ms.
The debounce circuitry eliminates switch-induced transients typically associated with electro-mechanical
devices including relays, proximity switches, and encoders.
From the following illustration we can see that there are two debounce modes, as well as a debounce
bypass. In addition, the signal from the buffer can be inverted before it enters the debounce circuitry. The
inverter is used to make the input rising-edge or falling-edge sensitive.
Edge selection is available with or without debounce. In this case the debounce time setting is ignored and
the input signal goes straight from the inverter [or inverter bypass] to the counter module.
There are 16 different debounce times. In either debounce mode, the debounce time selected determines
how fast the signal can change and still be recognized.
The two debounce modes are “trigger after stable” and “trigger before stable.” A discussion of the two
modes follows.
Debounce Model
DaqBoard/3000 Series User’s Manual 918494 Counter Input Modes 5-1