Omega Engineering PCI-DIO96 5.4.2 Group 1 8255 Configuration & Data

Table 5-3. DIO Port Configurations/Per Group

ININININ1559B1111 OUTINININ1549A0111 ININOUTIN153991011 OUTINOUTIN152980011 INOUTININ147931101 OUTOUTININ146920101 INOUTOUTIN145911001 OUTOUTOUTIN144900001 INININOUT1398B1110 OUTININOUT1388A0110 ININOUTOUT137891010 OUTINOUTOUT136880010 INOUTINOUT131831100 OUTOUTINOUT130820100 INOUTOUTOUT129811000 OUTOUTOUTOUT128800000 CLCUBADecHexD0D1D3D4 ValuesProgramming Codes

Notes: ‘CU’ is PORT C upper nibble, ‘CL’ is PORT C lower nibble.

5.4.2 Group 1 8255 Configuration & Data

GROUP 1, PORT A DATA

BADR3 + 4

READ/WRITE

D0D1D2D3D4D5D6D7

01234567

GROUP 1, PORT B DATA

BADR3 + 5

READ/WRITE

D0D1D2D3D4D5D6D7

01234567

GROUP 1, PORT C DATA

BADR3 + 6

READ/WRITE

CL1CL2CL3CL4CH1CH2CH3CH4

C1C2C3C4C5C6C7C8

01234567

Contents

Main Page Page 1 INTRODUCTION Figure 1-1. PCI-DIO96 Block Diagram 1 PCI-DIO96 Block Diagram 2 INSTALLATION 3 I/O CONNECTIONS 3.1 CABLES AND SCREW TERMINAL BOARDS 3.2 CONNECTOR DIAGRAM Figure 3-1. PCI-DIO96 100-Pin Connector Pin Out 3 Figure 3-2. Cable C100FF-xx Configuration 4 Figure 3-3. Pin Translation - Pins 51 to 100 DI/O Signals Group3 Group2 5 Group3 3.3 SIGNAL CONNECTION CONSIDERATIONS 3.4 CIO-ERB24 & SSR-RACK24 CONNECTIONS 4 SOFTWARE 4.1 UNIVERSAL LIBRARY 4.2 PACKAGED APPLICATION PROGRAMS 5 REGISTER MAPS 5.1 BADR0 5.2 BADR1 5.2.1 INTCSR Configure 5.3 BADR2 5.4 BADR3 5.4.1 Group 0 8255 Configuration & Data Page 5.4.2 Group 1 8255 Configuration & Data 5.4.3 Group 2 8255 Configuration & Data 5.4.4 Group 3 8255 Configuration & Data 5.4.5 8254 Configuration & Data 5.4.6 8255 Interrupt Source Configure 5.4.7 Counter Interrupt Source Configure 6 SPECIFICATIONS Power Consumption Digital Input / Output Counter Section Interrupts Crystal Oscillator Environmental Mechanical 7 ELECTRONICS AND INTERFACING 7.1 PULL UP & PULL DOWN RESISTORS 7.2 TTL TO SOLID STATE RELAYS 7.3 VOLTAGE DIVIDERS