Omega Engineering PCI-DIO96 user manual 6 8255 Interrupt Source Configure, Counter Configuration

Models: PCI-DIO96

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COUNTER CONFIGURATION

BADR3 + 13 hex

READ/WRITE

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

D7

D6

D5

D4

D3

D2

D1

D0

 

 

 

 

 

 

 

 

This register is used to set the operating modes of each of the 82C54’s counters. Configure the counters by writing mode information to the Configure register, followed by the count information written to the specific counter (data) registers. Refer to the Celeritous 82C54 data sheets for more detailed information.

5.4.6 8255 Interrupt Source Configure

BADR3 + 14 hex

READ/WRITE

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

DIRQ1

DIRQ0

CIRQ1

CIRQ0

BIRQ1

BIRQ0

AIRQ1

AIRQ0

 

 

 

 

 

 

 

 

DIRQ1

When this bit is set, the 8255 in Group 3 will generate an interrupt on

 

INTRB if INTEN in BASE +15 hex is also set.

 

 

DIRQ0

When this bit is set, the 8255 in Group 3 will generate an interrupt on

 

INTRA if INTEN in BASE +15 hex is also set.

 

 

CIRQ1

When this bit is set, the 8255 in Group 2 will generate an interrupt on

 

INTRB if INTEN in BASE +15 hex is also set.

 

 

CIRQ0

When this bit is set, the 8255 in Group 2 will generate an interrupt on

 

INTRA if INTEN in BASE +15 hex is also set.

 

 

BIRQ1

When this bit is set, the 8255 in Group 1 will generate an interrupt on

 

INTRB if INTEN in BASE +15 hex is also set.

 

 

BIRQ0

When this bit is set, the 8255 in Group 1 will generate an interrupt on

 

INTRA if INTEN in BASE +15 hex is also set.

 

 

AIRQ1

When this bit is set, the 8255 in Group 0 will generate an interrupt on

 

INTRB if INTEN in BASE +15 hex is also set.

 

 

AIRQ0

When this bit is set, the 8255 in Group 0 will generate an interrupt on

 

INTRA if INTEN in BASE +15 hex is also set.

 

 

16

Page 19
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Omega Engineering PCI-DIO96 user manual 6 8255 Interrupt Source Configure, Counter Configuration