Omega Engineering PCI-DIO96 user manual Register Maps, Intcsr Configure

5 REGISTER MAPS

The PCI Controller, a PLX-9052, has four configuration, control, and status registers (Table 5-1). They are described in the following section.

Table 5-1. I/O Region Register Operations

I/O Region	Function	Operations
BADR0	PCI memory-mapped configuration	32-bit double word
	registers
BADR1	PCI I/O-mapped config. registers	32-bit double word
BADR2	N/A	N/A
BADR3	Digital I/O registers	8-bit byte

5.1 BADR0

BADR0 is reserved for the PLX-9052 configuration registers. There is no reason to access this region of I/O space.

5.2 BADR1

BADR1 is a 32 bit register for control and configuration of interrupts.

5.2.1	INTCSR Configure
BADR1 +4C hex
32:15		14		13		12		11		10		9		8
X		X		X		ISAMD		X		INTCLR		X		LEVEL/EDGE
READ/WRITE
7			6		5		4		3		2		1		0
X			PCINT		X		X		X		INT		INTPOL		INTE

Note: For applications requiring edge triggered interrupts (LEVEL/EDGE bit 8 = 1), the user must configure the INTPOL bit for active high polarity (bit 1=1).

The INTCSR (Interrupt Control/Status Register) controls the interrupt features of the PLX-9052 controller. As with all of the PLX-9052 registers, it is 32-bits in length. Since the rest of the register have specific control functions, those bits must be masked off in order to access the specific interrupt control functions listed below.

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