Philips P89LPC901, P89LPC902, P89LPC903

Philips Semiconductors User’s Manual - Preliminary -

P89LPC901/902/903

TIMERS 0 AND 1

2003 Dec 8 50

Contents

Main Page 6. Real-Time Clock/System Timer............................................................ 51 7. Power Monitoring Functions................................................................. 55 Page Page Page 1. GENERAL DESCRIPTION P89LPC903 Pin Configurations 8-Pin Packages P89LPC901 P89LPC901/902/903 Logic Symbols Product comparison The following table highlights differences between these three devices. P89 LPC901 P89LPC901/902/903 Page Page PIN DESCRIPTIONS - P89LPC901 Page PIN DESCRIPTIONS - P89LPC902 PIN DESCRIPTIONS - P89LPC903 SPECIAL FUNCTION REGISTERS Special Function Registers Table - P89LPC901 Page Page Special Function Registers Table - P89LPC902 Page Page Special Function Registers Table - P89LPC903 Page Page Page Page 2. CLOCKS Oscillator Option Selection- P89LPC901 * Clock Output - P89LPC901 On-Chip RC oscillator Option Watchdog Oscillator Option External Clock Input Option - P89LPC901 Page Page CPU Clock (CCLK) Wakeup Delay CPU Clock (CCLK) Modification: DIVM Register Page Page 3. INTERRUPTS Interrupt Priority Structure Page External Interrupt Inputs External Interrupt Pin Glitch Suppression Figure 3-2: Interrupt sources, enables, and Power down Wake-up sources - P89LPC902 Figure 3-3: Interrupt sources, enables, and Power down Wake-up sources - P89LPC903 4. I/O PORTS Port Configurations Quasi-Bidirectional Output Configuration Open Drain Output Configuration Input-Only Configuration Push-Pull Output Configuration Port 0 Analog Functions Table 4-3: Port Output Configuration - P89LPC901 Table 4-4: Port Output Configuration - P89LPC902 Additional Port Features Page Page 5. TIMERS 0 AND 1 Mode 0 Mode 2 Mode 3 Mode 6 - P89LPC901 Page Timer Overflow toggle output - P89LPC901 Page 6. REAL-TIME CLOCK/SYSTEM TIMER Real-time Clock Source Reload on u nderflow 7-bit prescaler Page Changing RTCS1-0 Real-time Clock Interrupt/Wake Up Reset Sources Affecting the Real-time Clock Page 7. POWER MONITORING FUNCTIONS Brownout Detection Power-On Detection Table 7-1: Brownout Options. Power Reduction Modes Page Page Page 8. UART (P89LPC903) Mode 0 Mode 1 Mode 2 Mode 3 SFR Space Baud Rate Generator and Selection Updating the BRGR1 and BRGR0 SFRs Framing Error Break Detect Page More About UART Mode 0 More About UART Mode 1 More About UART Modes 2 and 3 Framing Error and RI in Modes 2 and 3 with SM2 = 1 Break Detect Double Buffering Double Buffering in Different Modes Transmit Interrupts with Double Buffering Enabled (Modes 1, 2 and 3) The 9th Bit (Bit 8) in Double Buffering (Modes 1, 2 and 3) Single Buffering (DBMOD/SSTAT.7 = 0), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown Multiprocessor Communications Automatic Address Recognition Page Page RESET 9. RESET Power-On reset code execution RESET 10. ANALOG COMPARATORS Comparator Configuration Figure 10-2: Comparator Input and Output Connections - P89LPC901 Figure 10-3: Comparator Input and Output Connections - P89LPC902 Internal Reference Voltage Comparator Interrupt Comparator and Power Reduction Modes Comparator Configuration Example 11. KEYPAD INTERRUPT (KBI) Page Page Page 12. WATCHDOG TIMER Watchdog Function Feed Sequence Page Table 12-2: P89LPC901/902/903 Watchdog Timeout Values Figure 12-3: Watchdog Timer in Watchdog Mode (WDTE = 1) 8-Bit Down Counter WDL (C1H) WDCON(A7H) Watchdog Timer in Timer Mode Power down operation Watchdog Clock Source Page Page Page ADDITIONAL FEATURES 13. ADDITIONAL FEATURES Software Reset Dual Data Pointers ADDITIONAL FEATURES 14. FLASH PROGRAM MEMORY General description Features Introduction to IAP-Lite Using Flash as data storage Page Page Accessing additional flash elements Erase-programming additional flash elements Reading additional flash elements Page User Configuration Bytes Page USER SECURITY BYTES Boot Vector Boot Status 15. INSTRUCTION SET Page Page Page REVISION HISTORY 16. REVISION HISTORY Page 17. INDEX Page Page Page Page Definitions Disclaimers Contact information