ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
Philips Semiconductors Preliminary Specification
1999 Nov 12 38
TABLE 17 Master Latency Timer Register - LATIME (RW)
TABLE 18 Header Type Register - HEADER (RO)
TABLE 19 BIST Register - BIST (RO)
PCI CFG 0D7D6D5D4D3D2D1D0
Offset 0Dh LATIME[7:0]
POR Value00000000
Bit Name R/W Function
7:0 LATIME RW The primary bus latency timer specifies the number of primary clocks that the
primary master may consume. The timer is reloaded at each assertion of
FRAME# by the primary master. If the primary master loses its bus grant,
then it must relinquish the bus after the timer expires.
PCI CFG 0D7D6D5D4D3D2D1D0
Offset 0Eh
MULTI_
FN
HEADER[6:0]
POR Value10000000
Bit Name R/W Function
7MULTI_FNROA 1 indicates that the SSA7785 ThunderBird Avenger™ is a multi-function
device. The three PCI configuration headers are accessed by the configura-
tion cycle address bits 10-8. The function definitions are as follows:
0 = Audio Subsystem
1 = Joystick
2 = 16650 UART
6:0 HEADER RO Header Type. A 00h indicates this device is a not a PCI-to-PCI bridge.
PCI CFG 0D7D6D5D4D3D2D1D0
Offset 0Fh BIST START R R CODE[3:0]
POR Value00000000
Bit Name R/W Function
7 BIST RO BIST capable. BIST is not supported in the SSA7785 ThunderBird
Avenger™, function 0 at this revision. It may be desired to include a BIST test
for the DSP at a later time.