ThunderBird AvengerTM PCI Audio SAA7785
Accelerator
Philips Semiconductors Preliminary Specification
1999 Nov 12 61
TABLE 61 BIST Register - BIST (RO)
SSA7785 ThunderBird Avenger™ CFG Space 1 Legacy Base Address Registers
The SSA7785 ThunderBird Avenger™, contains one legacy I/O base registers in configuration space 1. The joystick is
the sole legacy I/O base address register and is documented here.
TABLE 62 16650 UART Base Address - UARTBASE (RW/RO)
Bit Name R/W Function
7 MULTI_FN RO For the SSA7785 ThunderBird Avenger™, function 2, this bit has no mean-
ing.
6:0 HEADER RO Header Type. A 00h indicates this device is not a PCI-to-PCI bridge.
PCI CFG 2D7D6D5D4D3D2D1D0
Offset 0Fh BIST START R R CODE[3:0]
POR Value00000000
Bit Name R/W Function
7 BIST RO BIST capable. BIST is not supported in the SSA7785 ThunderBird
Avenger™, function 2 at this revision.
6 START RO If BIST capable, this bit will start the BIST. Writing a 1 will start the test and
the BIST should write this bit to a zero when complete. Software should fail
the device if the BIST is not complete after 2 seconds.
5:4 R RO Reserved. These bits always return zero.
3:0 CODE RO Completion Code. A value of zero means the device has passed its test.
Non-zero values means the device has failed using device specific failure
codes.
PCI CFG 2 D31 D30 D29 D28 D27 D26 D25 D24
Offset 10h UARTBASE[31:24]
POR Value00000000
D23 D22 D21 D20 D19 D18 D17 D16
UARTBASE[23:16]
POR Value00000000
D15 D14 D13 D12 D11 D10 D9 D8