Pioneer DV-535 Xmdrcas, XMDRDQM1, Xextrdy, Vss Gnd Cpu, Hrw, Xmdrwe, Hclkin, XMDRDQM0, Xhcs, Xhas

DV-535

No.	Pin Name	I/O	Function	No.	Pin Name	I/O	Function
131	VDD	−	2.5V power supply	170	XMDRCAS	O	CAS signal for SDRAM
132	XINT0	O	Interrupt request signal to CPU	171	XMDRDQM1	O	Input mask / output enable signal for
							SDRAM
			SPARC, 68 system : Ready signal to CPU
133	XEXTRDY	O	86 system : Acknowledge (ACK) signal to	172	VSS	−	GND
			CPU
134	HRW	I	CPU read / write signal	173	XMDRWE	O	Write enable signal for SDRAM
135	HCLKIN	I	Host clock input	174	XMDRDQM0	O	Input mask / output enable signal for
							SDRAM
136	XHCS	I	LSI chip select signal	175	MDRDAT8	I/O	Data bus signal for SDRAM
137	XHAS	I	SPARC, 68 system : CPU address strobe	176	VSS	−	GND
			86 system : CPU address status
138	XHBE3			177	MDRDAT7
139	XHBE2	I	CPU byte enable signal	178	MDRDAT9
140	XHBE1			179	MDRDAT6	I/O	Data bus signal for SDRAM
141	XHBE0			180	MDRDAT10
142	VSS	−	GND	181	MDRDAT5
143	MDRADR4			182	VSS	−	GND
144	MDRADR3	O	Address signal for SDRAM	183	VDD	−	2.5V power supply
145	MDRADR5			184	MDRDAT11
146	MDRADR2			185	MDRDAT4
147	VDD	−	2.5V power supply	186	MDRDAT12	I/O	Data bus signal for SDRAM
148	VSS	−	GND	187	MDRDAT3
149	MDRADR6			188	MDRDAT13
150	MDRADR1		Address signal for SDRAM	189	VSS	−	GND
151	MDRADR7	O		190	MDRDAT2
152	MDRADR0		Address signal for SDRAM (LSB)	191	MDRDAT14	I/O	Data bus signal for SDRAM
153	MDRADR8		Address signal for SDRAM	192	MDRDAT1
154	VSS	−	GND	193	MDRDAT15		Data bus signal for SDRAM (MSB)
155	TEST6			194	MDRDAT0	I/O	Data bus signal for SDRAM (LSB)
156	TEST7	I	"L" status normally	195	VSS	−	GND
157	TEST8			196	N.C.	−	Non connection
158	TEST9			197	ICK27M	I	System clock input
159	MDRADR10		Address signal for SDRAM	198	VSS	−	GND
160	MDRADR9	O		199	OCK27M	O	System clock output
161	MDRADR11		Address signal for SDRAM (MSB)	200	VSSA(VCO)	−	GND (for VCO only)
162	XMDRCS	O	Chip select signal for SDRAM	201	VDDA(VCO)	−	2.5V power supply (for VCO only)
163	MDRCKE	O	Clock enable signal for SDRAM	202	ILPF	O	PLL block inverter output for audio
164	VSS	−	GND	203	MLPF	I	PLL block inverter input for audio
165	VDD	−	2.5V power supply	204	OLPF	O	Phase detector output for audio
166	XMDRRAS	O	RAS signal for SDRAM	205	OVCO	I	VCO input for audio clock
167	MDRCLK	O	Clock output signal for SDRAM	206	VSS	−	GND
168	VSS	−	GND	207	XPLLRST	I	PLL section reset signal
169	MDRCLKIN	I	Clock input signal for SDRAM	208	XSYNCRST	I	SYNC reset signal

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