Released

PM5354

S/UNI MULTI 2x12

Multi-rate SATURN User Network Interface for 2x622 and 4x155

FEATURES

Single chip ATM and POS User Network Interface that supports up to 2x622.08 Mbit/s, 4x155.52 Mbit/s, 1x622.08 + 3x155.52 Mbit/s, or 2x622.08 Mbit/s + 2x155.52 Mbit/s.

Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.

Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 2615(1619)/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF).

Processes up to two duplex bit-serial 622.08 Mbit/s STS-12 (STM-4) data streams with on-chip clock and data recovery and clock synthesis. Each STS-12 (STM-4) may contain a single

STS-12c (AU-4-4c) or up to four STS-3c (AU-4).

Processes up to four duplex bit-serial 155.52 Mbit/s STS-3 (STM-1) data streams with on-chip clock and data recovery and clock synthesis. Each STS-3 (STM-1) may contain a single STS-3c (AU-4).

Permits mixed OC-12 and OC-3 data streams.

Complies with Telcordia GR-253-CORE jitter tolerance, jitter transfer, and intrinsic jitter criteria.

Provides termination for SONET Section, Line, and Path overhead or SDH Regenerator Section, Multiplexer Section, and High Order Path overhead.

Provides cross bar functionality to swap STS-12 and STS-3 clients to/from different line-side interfaces.

Provides support for automatic protection switching via a 4-bit LVDS 777.6 MHz port.

Provides cross bar functionality to swap STS-12 and STS-3 lines and/or clients to/from different APS interfaces.

Provides UTOPIA Level 3 32-bit wide System Interface (clocked up to 104 MHz) with parity support for ATM applications.

Provides SATURN® POS-PHY™ Level 3 (32-bit System Interface (clocked up to 104 MHz) for Packet over SONET (POS) or ATM applications.

Supports independent loop-timed operation for each transmit serial stream.

BLOCK DIAGRAM

TTOH[4:1] TTOHEN[4:1] TTOHFP[4:1] TTOHCLK[4:1]

 

 

 

APSI P/N[4:1]

 

 

 

 

 

 

 

 

 

 

 

 

SYSCLK

 

 

APSIFP

 

 

 

 

 

 

 

 

 

 

LINE_IF

 

 

 

 

LVDS I/f

SONET/APS

 

 

 

 

 

PL3/UL3

 

 

 

Transmit

 

Transmit

 

(4)

 

 

 

 

 

 

 

 

 

 

 

 

Section

 

Path

 

Receive

 

 

 

 

 

 

 

 

 

 

 

Trace

 

Trace

 

APS

 

 

 

 

 

 

 

 

 

 

 

 

Processor

 

Processor

 

(4)

 

 

 

 

 

 

 

 

 

 

 

 

(4)

 

(4)

 

X-Bar

 

 

 

 

 

 

 

 

 

STPA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCA/PTPA

TXD_P/N[4:1]

Transmit Analog

Transmit

Transmit

 

 

 

 

 

 

 

 

 

 

 

UTOPIA L3/

TADR[3:0]

Circuitry

Transmit

 

 

 

In

 

 

Transmit

Transmit

 

TENB

 

Regen/

Virtual

 

 

 

 

 

 

POS-PHY

TSX

 

Transmit

Path

 

 

 

band

 

Transmit

channel

ATM/POS

Transmit

 

Line

Multiplexor

Container

 

 

 

 

L3

TSOC/TSOP

 

Processor

 

 

 

Alarm

PRBS

X-Bar

Assigner

processor

FIFO

 

Interface

Processor

Aligner

 

 

 

Transmit

TEOP

 

(4)

 

 

 

(4)

generator

 

(4)

 

(4)

 

 

 

(4)

(4)

 

 

 

 

 

 

Interface

TDAT[31:0]

 

 

 

 

 

 

 

/ monitor

 

 

 

 

 

TPRTY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(4)

 

 

 

 

 

 

TMOD[1:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TERR

 

 

SARC

 

 

 

 

 

 

 

 

 

 

 

 

 

TFCLK

 

 

Alarm Report

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

Controller (4)

 

 

 

 

 

 

 

 

 

 

 

 

PL3EN

REFCLK77_P/N

Synthesis

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit error

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rate mon

 

 

 

 

 

 

 

 

 

 

 

 

 

RADR[3:0]

 

 

(4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RENB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RFCLK

 

 

Receive

Receive

Receive

 

 

 

 

 

 

Receive

Receive

 

UTOPIA L3/

RDAT[31:0]

 

Receive

Regen/

Virtual

 

 

 

 

 

Receive

 

POS-PHY

 

Path

 

 

 

 

 

channel

ATM/POS

Receive

RCA/RVAL

 

Line

Multiplexor

Container

 

 

 

 

 

X-Bar

L3

 

Processor

 

 

 

 

 

Assigner

processor

FIFO

RPRTY

 

Interface

Processor

Aligner

 

 

 

 

 

 

Receive

 

(4)

 

 

 

 

 

 

(4)

 

(4)

 

RSX

 

Receive Analog

(4)

(4)

 

 

 

 

 

 

 

 

Interface

RXD_P/N[4:1]

 

 

 

 

 

 

 

 

RSOC/RSOP

Circuitry

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X-Bar

 

 

 

 

 

 

 

 

 

RMOD[1:0]

 

 

Receive

Receive

 

 

 

 

 

 

 

 

 

 

RERR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Section

Path

 

Transmit

 

 

 

 

 

 

 

 

 

 

SD[4:1]

 

Trace

Trace

 

 

APS

 

 

 

 

 

 

 

 

 

 

 

Processor

Processor

 

 

(4)

 

 

 

 

 

 

 

 

 

 

SD_TEST

 

 

 

 

 

 

 

Microprocessor

 

JTAG

 

 

 

(4)

(4)

 

LVDS I/f

 

 

 

 

 

 

 

 

 

 

 

 

 

(4)

 

 

 

 

Interface

 

 

Interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RCLKO

RTOHFP[4:1] RTOH[4:1] RTOHCLK[4:1]

SALM[4:1] RALM[4:1] B3E[4:1]

 

APSO P/N[4:1]

APSOFP

 

 

 

D[15:0]

A[13:0] WRB RDB ALE CSB RSTB

INTB

TCK TDI TMS TRSTB

TDO

 

PMC-2021540 (R3)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

© Copyright PMC -Sierra, Inc. 2003

Page 1
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PMC-Sierra PM5354 manual Features, Block Diagram

PM5354 specifications

The PMC-Sierra PM5354 is a highly integrated device designed for telecommunications and data networking applications. This versatile chip is part of the PMC-Sierra family of networking solutions, which are renowned for their ability to handle complex data processes efficiently. The PM5354 is particularly tailored for applications such as Ethernet and SONET/SDH, making it an ideal choice for service provider networks and enterprise environments.

One of the key features of the PM5354 is its ability to support high-speed data transmission. The device operates at speeds of up to 10 Gbps, making it suitable for high-bandwidth applications and ensuring that network operators can meet the demands of their customers seamlessly. The chip incorporates advanced packet processing capabilities, allowing it to manage large volumes of data traffic with minimal latency.

The PM5354 also supports multiple physical-layer (PHY) interfaces, which enhances its flexibility in various network configurations. This chip can be implemented in systems that require compatibility with different standards, such as Gigabit Ethernet and 10 Gigabit Ethernet. The multi-rate support allows system designers to create solutions that are not only robust but also cost-effective.

Another notable characteristic of the PM5354 is its performance in quality of service (QoS). The device integrates sophisticated QoS features, enabling it to prioritize traffic efficiently, which is crucial for applications that require real-time data transmission such as VoIP and video conferencing. This capability ensures that critical data packets are transmitted without delay, leading to improved user experiences.

The PM5354 also emphasizes power efficiency, which is vital for modern networking equipment designed to minimize energy consumption. By leveraging low-power technologies, this chip significantly reduces the overall power requirements of the network devices, allowing operators to lower operational costs while adhering to environmental standards.

In addition to its hardware features, the PM5354 includes an extensive set of software tools that facilitate easy integration with existing network equipment. It supports various management protocols, making it simpler for network administrators to deploy, monitor, and maintain their systems.

In summary, the PMC-Sierra PM5354 is a cutting-edge networking solution that combines high-speed processing, adaptability, quality of service excellence, and power efficiency. Its multifaceted features make it a compelling choice for enterprises and service providers looking to enhance their network performance and reliability.