Rev. 1.00, 05/04, page 523 of 544
22.3.3 Timing of On-Chip Peripheral Modules
Tables 22.7 to 22.10 show the on-chip peripheral module timing. The only on-chip peripheral
modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external
interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and
1).
Table 22.7 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz*,
4 MHz to maximum operating frequency, Ta = –20 to +75°C
Condition
10 MHz
Item Symbol
Min. Max. Unit Test
Conditions
Output data delay time tPWD — 100
Input data setup time tPRS 50 —
I/O ports
Input data hold time tPRH 50 —
ns Figure 22.10
Timer output delay time tFTOD — 100
Timer input setup time tFTIS 50 —
Figure 22.11
Timer clock input setup time tFTCS 50 —
ns
Single edge tFTCWH 1.5 —
FRT
Timer clock
pulse width Both edges tFTCWL 2.5 —
tcyc
Figure 22.12
Timer output delay time tTMOD — 100 Figure 22.13
Timer reset input setup time tTMRS 50 — Figure 22.15
Timer clock input setup time tTMCS 50 —
ns
Single edge tTMCWH 1.5 —
TMR
Timer clock
pulse width Both edges tTMCWL 2.5 —
tcyc
Figure 22.14
PWM Pulse output delay time tPWOD — 100 ns Figure 22.16
Asynchronous tScyc 4 — Input clock
cycle Synchronous 6 —
tcyc
Input clock pulse width tSCKW 0.4 0.6 tScyc
Input clock rise time tSCKr — 1.5
SCI
Input clock fall time tSCKf — 1.5
tcyc
Figure 22.17