Rev. 1.00, 05/04, page 525 of 544
Table 22.9 I2C Bus Timing
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency,
Ta = –20 to +75°C
Ratings
Item Symbol Min. Typ. Max. Unit
Test
Conditions Notes
SCL input cycle time tSCL 12 — — tcyc
SCL input high pulse width tSCLH 3 — — tcyc
SCL input low pulse width tSCLL 5 — — tcyc
SCL, SDA input rise time tSr — — 7.5* t
cyc
SCL, SDA input fall time tSf — — 300 ns
SCL, SDA input spike pulse
elimination time
tSP — — 1 tcyc
SDA input bus free time tBUF 5 — — tcyc
Start condition input hold time tSTAH 3 — — tcyc
Retransmission start condition
input setup time
tSTAS 3 — — tcyc
Stop condition input setup time tSTOS 3 — — tcyc
Data input setup time tSDAS 0.5 — — tcyc
Data input hold time tSDAH 0 — — ns
SCL, SDA capacitive load Cb — — 400 pF
Figure
22.22
Note: * 17.5 tcyc can be set according to the clock selected for use by the I2C module. For
details, see section 13.6, Usage Notes.