Rev. 1.00, 05/04, page 526 of 544
Table 22.10 LPC Module Timing
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 4 MHz to maximum operating frequency,
Ta = –20 to +75°C
Item Symbol Min. Typ. Max. Unit
Test
Conditions
Input clock cycle tLcyc 30 — —
Input clock pulse width (H) tLCKH 11 — —
Input clock pulse width (L) tLCKL 11 — —
Transmit signal delay time tTXD 2 — 11
Transmit signal floating
delay time
tOFF — — 28
Receive signal setup time tRXS 7 — —
LPC
Receive signal hold time tRXH 0 — —
ns Figure 22.23
22.4 A/D Conversion Characteristics
Tables 22.11 list the A/D conversion characteristics.
Table 22.11 A/D Conversion Characteristics (AN5 to AN0 Input: 134/266-State Conversion)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC,
VCCB = 3.0 V to 5.5 V, VSS = AVSS = 0 V,
φ = 4 MHz to maximum operating frequency, Ta = –20 to +75°C
Condition
10 MHz
Item Min. Typ. Max. Unit
Resolution 10 bits
Conversion time — — 13.4 µs
Analog input capacitance — — 20 pF
Permissible signal-source impedance — — 5 kΩ
Nonlinearity error — — ±7.0 LSB
Offset error — — ±7.5 LSB
Full-scale error — — ±7.5 LSB
Quantization error — — ±0.5 LSB
Absolute accuracy — — ±8.0 LSB