Renesas HD151TS207SS Pin Descriptions (cont.)

HD151TS207SS

Rev.1.00, Apr.25.2003, page 5 of 38

Pin Descriptions (cont.)

Pin name No. Type Description

PWRDWN#/

SAFE_F# 21 INPUT

PULL–UP* PWRDWN# / SAFE_F# selectable input.

Default is PWRDWN# input.

Byte15[5] = “1” : SAFE_F# input.

PWRDWN# is all clocks stop pin.

Asynchronous active “Low” input.

When asserted low, all output clocks are disabled.

SAFE_F# is active “Low” input.

When SAFE_F# is “Low” ,frequency mode is changed to the

predefined frequency mode.

3V66_0/RESET# 22 OUTPUT 3V66 / Watchdog RESET# selectable output.

Default is 3V66 output.

This signal is active low and selected by Mode latch input.

3V66_[1:3] 23,26,

27 OUTPUT 3V66 clock 3.3V outputs.

SCLK 28 INPUT

PULL-UP* Clock input for I2C logic.

**SEL66_48/

3V66_4/VCH 29 INPUT/

OUTPUT Latched select input for 3V66/VCH output 1 = 48 MHz,

0 = 66.66 MHz. /3V66 or VCH clock output.

SDATA 30 IN/OUTPUT

PULL-UP* Data input for I2C logic.

**SEL48_24/

USB_48 31 INPUT/

OUTPUT Latched select input for 48_24 MHz output

1 = 24 MHz, 0 = 48 MHz / 24_48 MHz clock 3.3 V output.

FS3/DOT_48 32 INPUT/

OUTPUT Frequency select latch input pin.

/DOT_48 clock 3.3 V output.

VTT_PWRGD# 35 INPUT

PULL-UP* Qualifying input that latches FS_A and FS_B.

When asserted low, FS_A and FS_B are latched.

SRC# 37 OUTPUT “Complementary” clock of Differential Serial Reference Clock.

SRC 38 OUTPUT “True” clock of Differential Serial Reference Clock.

CPU_[0:2]# 40,43,

46 OUTPUT “Complementary” clock of differential CPU clock.

CPU_[0:2] 41,44,

47 OUTPUT “True” clock of differential CPU clock.

PCI_STOP# 49 INPUT

PULL–UP* PCI clocks stop pin. Active “Low” input.

When asserted low, PCI[6:0] and SRC clocks are

synchronously disabled in low state.

Usually this pin does not give to effect PCIF[2:0] clock outputs.

TEST_CLK# 50 INPUT

PULL-UP* Test clock mode pin. Active “Low” input.

FS_[A:B] 51,52 INPUT CPU clocks frequency select latch input.

IREF 52 INPUT A precision resistor is attached to this pin which is connected

to internal current reference.

A resistor is connected between this pin and GNDIREF.

Note: (*): Those pins are 150 kΩ internal pulled-UP.

(**): Those pins are 150 kΩ internal pulled-DOWN

Contents

Main HD151TS207SS Mother Board Clock Generator for Intel P4+ Chipset (Springdale) Description Features Page Rev.1.00, Apr.25.2003, page 3 of 38 Pin Arrangement PCI_STOP#, PWRDWN# = 150 k Internal Pull-up Pin Descriptions HD151TS207SS Pin Descriptions (cont.) Block Diagram * : Latched Input pin. HD151TS207SS I2C Controlled Register Bit Map Byte0 Control Register Table1 Clock Frequency Function Table Table2 Test Clock select table Table3 FS_A and FS_B pin Input level Byte1 Control Register Byte2 Control Register Table4 CPU Clock Power Management Truth Table Table5 SRC Clock Power Management Truth Table Byte3 Control Register Byte4 Control Register Byte5 Control Register Byte6 Control Register Byte7 Vendor Identification Register Byte8 Read Back Byte Count Register Byte9 Control Register Table6 Clock Frequency Function Table Byte10 Control Register Byte11 Control Register HD151TS207SS Byte12 Control Register Byte13 Control Register Byte14 Control Register Byte15 Control Register Byte16 Control Register How to set VCO2 frequency to 666 MHz. How to read actual frequency of VCO2 and CPU clock Byte20 Control Register Byte21 Control Register HD151TS207SS Byte22 Control Register Byte23 Control Register Byte24 Control Register Byte25 Control Register Byte26 Control Register Byte27 Control Register Byte28 Control Register Byte29 Control Register Clock Stop Timing Diagram PCI_STOP# Assertion/De-assersion PWRDWN# Assertion/De-assersion Renesas clock generator I2C Serial Interface Operation Renesas clock generator I2C Serial Interface Operation (cont.) Absolute Maximum Ratings Recommended Operating Conditions DC Electrical Characteristics / Serial Input Port AC Electrical Characteristics / Serial Input port DC Electrical Characteristics CPU/CPU# Clock Ta = 0C to 70C, VDD = 3.3 V, Iref = 475 AC Electrical Characteristics CPU/CPU# Clock (CPU at 0.7V Timing) Ta = 0C to 70C, VDD = 3.3 V, CL = 2 pF, Rs = 33.2 , Rp = 49.9 DC Electrical Characteristics SRC/SRC# Clock Ta = 0C to 70C, VDD = 3.3 V, Iref = 475 AC Electrical Characteristics SRC/SRC# Clock (SRC at 0.7V Timing) Ta = 0C to 70C, VDD = 3.3 V, CL = 2 pF, Rs = 33.2 , Rp = 49.9 DC Electrical Characteristics / 3V66 Buffer (CK409T Type5 Buffer) AC Electrical Characteristics / 3V66 Buffer DC Electrical Characteristics / PCI & PCIF Clock (CK409T Type5 Buffer) AC Electrical Characteristics / PCI & PCIF Clock DC Electrical Characteristics / USB & VCH 48MHz Clock (CK409T Type3A Buffer) AC Electrical Characteristics / USB & VCH 48MHz Clock Ta = 0C to 70C, VDD = 3.3 V, CL = 20 pF DC Electrical Characteristics / DOT Clock (CK409T Type3B Buffer) AC Electrical Characteristics / DOT Clock Ta = 0C to 70C, VDD = 3.3 V, CL = 10 pF DC Electrical Characteristics / REF Clock (CK409T Type5 Buffer) AC Electrical Characteristics / REF Clock Clock Out tcycle n t = (tcycle n) - (tcycle n+1) tcycle n+1 Fig.1 Cycle to Cycle Jitter (3.3V Single Ended Clock Output) Fig.2 Output Clock Skew (3.3V Single Ended Clock Output) Fig.3 Load Circuit for CPU/CPU# Package Dimensions Unit : mm Rev.1.00, Apr.25.2003, page 38 of 38 Keep safety first in your circuit designs! Colophon 0.0 http://www.renesas.com Copyright 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.