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Renesas HD151TS207SS Table3 FS_A and FS_B pin Input level, Byte1 Control Register, Byte2 Control Register

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HD151TS207SS

Rev.1.00, Apr.25.2003, page 8 of 38

I2C Controlled Register Bit Map (cont.)

Table3 FS_A and FS_B pin Input level

Logic Level Min Voltage Max Voltage

0 (Low) 0.35V

1 (High) 0.70V 

Byte1 Control Register

Bit Description Contents Type Default Note

7 Allow control of SCR with assertion

of PCI_STOP# 0 = Free running

1 = Stopped with

PCI_STOP#

RW 0 See

Table5

6 SRC Output enable 0 = Disabled (tristate)

1 = Enabled RW 1

5 Reserved RW 1

4 Reserved RW 1

3 Reserved RW 1

2 CPU2 Output enable 0 = Disabled (tristate)

1 = Enabled RW 1

1 CPU1 Output enable 0 = Disabled (tristate)

1 = Enabled RW 1

0 CPU0 Output enable 0 = Disabled (tristate)

1 = Enabled RW 1

Byte2 Control Register

Bit Description Contents Type Default Note

7 SRC_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate RW 0

6 SRC_Stop drive mode 0 = Driven when stopped,

1 = Tristate RW 0

See

Table5

5 CPU2_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate RW 0

4 CPU1_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate RW 0

3 CPU0_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate RW 0

2 Reserved RW 0

1 Reserved RW 0

0 Reserved RW 0

See

Table4

Contents

Main HD151TS207SS Mother Board Clock Generator for Intel P4+ Chipset (Springdale) Description Features Page Rev.1.00, Apr.25.2003, page 3 of 38 Pin Arrangement PCI_STOP#, PWRDWN# = 150 k Internal Pull-up Pin Descriptions HD151TS207SS Pin Descriptions (cont.) Block Diagram * : Latched Input pin. HD151TS207SS I2C Controlled Register Bit Map Byte0 Control Register Table1 Clock Frequency Function Table Table2 Test Clock select table Table3 FS_A and FS_B pin Input level Byte1 Control Register Byte2 Control Register Table4 CPU Clock Power Management Truth Table Table5 SRC Clock Power Management Truth Table Byte3 Control Register Byte4 Control Register Byte5 Control Register Byte6 Control Register Byte7 Vendor Identification Register Byte8 Read Back Byte Count Register Byte9 Control Register Table6 Clock Frequency Function Table Byte10 Control Register Byte11 Control Register HD151TS207SS Byte12 Control Register Byte13 Control Register Byte14 Control Register Byte15 Control Register Byte16 Control Register How to set VCO2 frequency to 666 MHz. How to read actual frequency of VCO2 and CPU clock Byte20 Control Register Byte21 Control Register HD151TS207SS Byte22 Control Register Byte23 Control Register Byte24 Control Register Byte25 Control Register Byte26 Control Register Byte27 Control Register Byte28 Control Register Byte29 Control Register Clock Stop Timing Diagram PCI_STOP# Assertion/De-assersion PWRDWN# Assertion/De-assersion Renesas clock generator I2C Serial Interface Operation Renesas clock generator I2C Serial Interface Operation (cont.) Absolute Maximum Ratings Recommended Operating Conditions DC Electrical Characteristics / Serial Input Port AC Electrical Characteristics / Serial Input port DC Electrical Characteristics CPU/CPU# Clock Ta = 0C to 70C, VDD = 3.3 V, Iref = 475 AC Electrical Characteristics CPU/CPU# Clock (CPU at 0.7V Timing) Ta = 0C to 70C, VDD = 3.3 V, CL = 2 pF, Rs = 33.2 , Rp = 49.9 DC Electrical Characteristics SRC/SRC# Clock Ta = 0C to 70C, VDD = 3.3 V, Iref = 475 AC Electrical Characteristics SRC/SRC# Clock (SRC at 0.7V Timing) Ta = 0C to 70C, VDD = 3.3 V, CL = 2 pF, Rs = 33.2 , Rp = 49.9 DC Electrical Characteristics / 3V66 Buffer (CK409T Type5 Buffer) AC Electrical Characteristics / 3V66 Buffer DC Electrical Characteristics / PCI & PCIF Clock (CK409T Type5 Buffer) AC Electrical Characteristics / PCI & PCIF Clock DC Electrical Characteristics / USB & VCH 48MHz Clock (CK409T Type3A Buffer) AC Electrical Characteristics / USB & VCH 48MHz Clock Ta = 0C to 70C, VDD = 3.3 V, CL = 20 pF DC Electrical Characteristics / DOT Clock (CK409T Type3B Buffer) AC Electrical Characteristics / DOT Clock Ta = 0C to 70C, VDD = 3.3 V, CL = 10 pF DC Electrical Characteristics / REF Clock (CK409T Type5 Buffer) AC Electrical Characteristics / REF Clock Clock Out tcycle n t = (tcycle n) - (tcycle n+1) tcycle n+1 Fig.1 Cycle to Cycle Jitter (3.3V Single Ended Clock Output) Fig.2 Output Clock Skew (3.3V Single Ended Clock Output) Fig.3 Load Circuit for CPU/CPU# Package Dimensions Unit : mm Rev.1.00, Apr.25.2003, page 38 of 38 Keep safety first in your circuit designs! Colophon 0.0 http://www.renesas.com Copyright 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.