HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 11 of 29
Detailed Timing Specifications when CDSIN Input Mode is Used
Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.
CDS_in
SP1 Vth
(2) (3)
SP2
A
DCLK
(7)
Vth
Vth
(8)
(9)
(10)
(4)
(1)
(5)
(11)
(6)
(13)
(12)
D0 to D9
H1
Black
level
Signal
level
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used
Table 8 Timing Specifications when the CDSIN Input Mode is Used
No. Timing Symbol Min Typ Max Unit
(1) Black-level signal fetch time tCDS1 — (1.5) — ns
(2) SP1 ‘Hi’ period tCDS2 Typ × 0.8 1/4fCLK Typ × 1.2 ns
(3) Signal-level fetch time tCDS3 — (1.5) — ns
(4) SP2 ‘Hi’ period tCDS4 Typ × 0.8 1/4fCLK Typ × 1.2 ns
(5) SP1 falling to SP2 falling time tCDS5 Typ × 0.85 1/2fCLK Typ × 1.15 ns
(6) SP1 falling to ADCLK rising inhibit time tCDS6 — (5) — ns
(7), (8) ADCLK tWH min./tWL min tCDS7, 8 11 — — ns
(9) ADCLK rising to digital output holding time t
CHLD9 — (7) — ns
(10) ADCLK rising to digital output delay time tCOD10 — (16) — ns
(11) H1 rising to ADCLK rising time tCDS11 — (1/4fCLK) — ns
(12) H1 rising to SPSIG falling time tCDS12 — (1/fCLK) — ns
(13) H1 rising to SPBLK falling time tCDS13 — (1/2fCLK) — ns
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black
signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard).
CDS_in
OBP
NN+1 N+5 N+12 N+13
Note:
OB pulse > 2 clock cycles
OB period *
1
1. Shifts ±1 clock cycle depending on the OBP input timing.