HD49335NP/HNP

Rev.1.0, Feb.12.2004, page 15 of 29

Electrical Characteristics (cont.)

(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)

• Items for CDSIN Input Mode

Item Symbol Min Typ Max Unit Test Conditions Remarks
Consumption current (1) IDD1 — 84 96.6 mA fCLK = 36 MHz CDSIN mode
LoPwr = low
Consumption current (2) IDD2 — 58 66.7 mA fCLK = 20 MHz CDSIN mode
LoPwr = high
CCD offset tolerance range VCCD (–100) — (100) mV
Timing specifications (1) tCDS1 — (1.5) — ns
Timing specifications (2) tCDS2 Typ × 0.8 1/4fCLK Typ × 1.2 ns
Timing specifications (3) tCDS3 — (1.5) — ns
Timing specifications (4) tCDS4 Typ × 0.8 1/4fCLK Typ × 1.2 ns
Timing specifications (5) tCDS5 Typ × 0.85 1/2fCLK Typ × 1.15 ns
Timing specifications (6) tCDS6 1 5 9 ns
Timing specifications (7) tCDS7 — 1/2fCLK — ns
Timing specifications (8) tCDS8 — 1/2fCLK — ns
Timing specifications (9) tCHLD9 — (7) — ns CL = 10 pF
Timing specifications (10) tCOD10 — (16) — ns CL = 10 pF
Timing specifications (11) tCDS11 — (1/4fCLK) — ns
Timing specifications (12) tCDS12 — (1/fCLK) — ns
Timing specifications (13) tCDS13 — (1/2fCLK) — ns
Refer to table 8
CLP(00) — (14) — LSB
CLP(09) — (32) — LSB
Clamp level
CLP(31) — (76) — LSB
AGC(0) –4.4 –2.4 –0.4 dB
AGC(63) 4.1 6.1 8.1 dB
AGC(127) 12.5 14.5 16.5 dB
AGC(191) 21.0 23.0 25.0 dB
PGA gain at CDS input
AGC(255) 29.4 31.4 33.4 dB
*1
DLL_2 11 — 25 MHz *2
DLL_3 7 — 11 MHz *3
DLL operation frequency
DLL_4 5.5 — 7 MHz *4
T/G 3/1divided operation
frequency range
CLK_in3 28.6 — 28.6 MHz fCLK = 1/3CLK_in3
VOH 2.94 2.97 — V 30 mA Buff, IOH = –5 mA
VOL — 22 47 MV 30 mA Buff, IOL = +5 mA
VOH 2.89 2.94 — V 14 mA Buff, IOH = –5 mA
VOL — 50 112 MV 14 mA Buff, IOL = +5 mA
VOH 2.91 2.96 — V 10 mA Buff, IOH = –3 mA
VOL — 36 78 MV 10 mA Buff, IOL = +3 mA
VOH 2.85 2.93 — V 4 mA Buff, I OH = –2 mA
VOL — 60 129 MV 4 mA Buff, IOL = +2 mA
VOH 2.69 2.86 — V 2 mA Buff, I OH = –2 mA
H Buffer output voltage
VOL — 115 262 mV 2 mA Buff, IOL = +2 mA
VOH 2.81 2.90 — V IOH = –2 mA RG output voltage
VOL — 78 141 mV IOL = +2 mA

Notes: 1. Define digital output full scall with 1 V input as 0 dB.

2. Number of master steps: 60 steps, DLL current High

3. Number of master steps: 40 steps, DLL current Low

4. Number of master steps: 60 steps, DLL current Low

5. Values within parentheses ( ) are for reference.