
Rev.1.0, Feb.12.2004, page 8 of 29
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X
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X
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X
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X
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X
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X
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X
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X
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STBY
D9
TEST0
D0D1D2D3D4D5D6D7D8
PBLK
MINV
TEST1
LINV
Hi-Z
Same as in table 4.
D9 is inverted in table 4.
D8 to D0 are inverted in table 4.
D9 to D0 are inverted in table 4.
Output code is set up to Clamp Level.
Same as in table 5.
D9 is inverted in table 5.
D8 to D0 are inverted in table 5.
D9 to D0 are inverted in table 5.
Output code is set up to Clamp Level.
Low-power wait state
Normal operation
Pre-blanking
Normal operation
Pre-blanking
Test mode
Operating Mode
ADC Digital Output
Note: 1. STBY, TEST, LINV, and MINV are set by register.
D1
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L
H
H
L
L
L
H
H
D0
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H
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H
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H
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H
D2
L
H
H
H
H
L
H
H
H
H
D7
L
L
L
L
H
L
H
H
H
H
D5
L
L
L
L
H
L
H
H
H
H
D4
L
L
L
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H
L
H
H
H
H
D3
L
L
L
L
H
L
H
H
H
H
D6
L
L
L
L
H
L
H
H
H
H
D8
L
L
L
L
H
L
H
H
H
H
D9
L
L
L
L
L
H
H
H
H
H
3
4
5
6
511
512
1020
1021
1022
1023
Output Pin
Output
codes
Steps
D8
L
L
L
L
H
H
L
L
L
L
D9
L
L
L
L
L
H
H
H
H
H
3
4
5
6
511
512
1020
1021
1022
1023
D1
H
H
H
L
L
L
H
H
L
L
D0
L
L
H
H
L
L
L
H
H
L
D2
L
H
H
H
L
L
L
L
L
L
D7
L
L
L
L
L
L
L
L
L
L
D5
L
L
L
L
L
L
L
L
L
L
D4
L
L
L
L
L
L
L
L
L
L
D3
L
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L
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L
L
L
L
L
L
D6
L
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L
L
L
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L
L
Output Pin
Output
codes
Steps