Sharp R-2397 2-2Memory IC IC2, Sound Voltage level control terminal, Pin No, Signal, Description

R-2397

Pin No.

Signal

I/O

Description

46

P10

OUT

Segment data signal.

Signal similar to P17.

47-48

P07-P06

OUT

Segment data signal.

Signal similar to P17.

49

P05

OUT

Digit selection signal.

H

The relation between digit signal and digit are as ß(50Hz)

L

follows:

Digit signal

Digit

GND

P05

1st.

P05

-31(V)

P04

2nd.

P04

P03

3rd.

P02

4th.

P03

P01

5th.

P00

6th.

P02

P01

Normally, one pulse is output in every ß period,

GND

and input to the grid of the Fluorescent Display.

P00

-31(V)

50-54

P04-P00

OUT

Digit selection signal.

Signal similar to P16.

55-57

P27-P25

OUT

Terminal not used.

58-59

P24-P23

OUT

Segment data signal.

Signal similar to P17.

60

P22

OUT

(Sound) Voltage level control terminal.

This terminal (P22) is to control volume level of buzzer sound with terminals P21. Since

the volume level of buzzer sound depends on voltage energized, it is control level in 3

steps by combining signal levels for P22,P21. Relationship of signal level combination to

sound volume level is shown in the following table, 1~3 in the table, however, are indicated

in the descending order from the maximum level of sound volume through the minimum

level.

Sound Volume

P21

P22

1,(Max.)

L

L

A A : 1,(Max) 20V

2,

13V

2,

H

L

3,(Min)

7V

3,(Min.)

L

H

*At Output terminal P32, rectangular wave signal of 2.5kHz is output.

61

P21

OUT

Sound level control signal.

Refer to above signal P22.

62

P20

IN

Input signal which communicates the door open/close information to LSI.

Door closed; "H" level signal(0V).

Door opened; "L" level signal(-31.0V).

63/64

AVCC/VCC

IN

Connected to GND.

2-2 Memory IC (IC2)

AT24C04 is a 4K-bit, serial memory, enabling CMOS to be erased/written electrically. This memory is constructed with 512 registers x 8bits, enabling individual access, read and write operations to be performed. Details of input/output signal for IC2 are as shown in the following diagram.

FUNCTIONAL DIAGRAM

	TOP VIEW
A0	1	8
	2	7
A1
A2	3	6
VSS	4	5

VCC

TEST

SCL

SDA

(3) Vcc
(4) Vss			START CYCLE	H.V. GENERATION
				TIMING
				& CONTROL
(5) SDA	START
	STOP
	LOGIC
	CONTROL
	LOGIC			E 2PROM
			64
	SLAVE ADDRESS			512 x 8
			XDEC
(6) SCL	REGISTER
	COMPARATOR
	LOAD	INC
	WORD
	ADDRESS		1	64
	COUNTER		5
	R/W		3	YDEC
			CK	8
	PIN				Dout
				DATA REGISTER
	Dout
	ACK

Figure T-4 Relation between Pin Nos, and Signals

20