SMC Networks A8V-X manual Burst Length 4 Beats, ECC Configuration, Dram ECC Enable Disabled

Configuration options: [4.0ns] [5.0ns] [6.0ns] [7.0ns] [8.0ns] [9.0ns] [10.0ns] [11.0ns]

CMD-ADDR Timing Mode [2T]

Sets the CMD-ADDR timing mode.

Configuration options: [1T] [2T]

Burst Length [4 Beats]

Allows you to set the burst length.

Configuration options: [8 Beats] [4 Beats] [2 Beats]

ECC Configuration

ECC Configuration

DRAM ECC	Enable	[Disabled]
L2 Cache	BG Scrub	[Disabled]
Data Cache BG Scrub		[Disabled]

DRAM ECC Enable [Disabled]

Allows you to enable or disable the DRAM ECC.

Configuration options: [Disabled] [Enabled]

The following items appear only when the DRAM ECC Enable is set to Enabled.

MCA DRAM ECC Logging [Disabled]

Enables or disables the MCA DRAM ECC logging.

Configuration options: [Disabled] [Enabled]

ECC Chip Kill [Disabled]

Enables or disables the ECC Chip Kill function.

Configuration options: [Disabled] [Enabled]

DRAM SCRUB REDIRECT [Disabled]

Enables or disables the DRAM SCRUB REDIRECT.

Configuration options: [Disabled] [Enabled]

2-22 Chapter 2: BIOS setup