Integrated USB 2.0 Compatible
Datasheet
5.3.4Slave Device Time-Out
According to the SMBus Specification, V1.0 devices in a transfer can abort the transfer in progress
and release the bus when any single clock low interval exceeds 25ms (TTIMEOUT, MIN). Devices that have detected this condition must reset their communication and be able to receive a new START
condition no later than 35ms (TTIMEOUT, MAX).
Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically resets its communications port after a start or stop condition.
5.3.5Stretching the SCLK Signal
The Hub supports stretching of the SCLK by other devices on the SMBus. The Hub does not stretch the SCLK.
5.3.6SMBus Timing
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing in the “Timing Diagram” section.
5.3.7Bus Reset Sequence
The SMBus Slave Interface resets and returns to the idle state upon a START field followed immediately by a STOP field.
5.3.8SMBus Alert Response Address
The SMBALERT# signal is not supported by the Hub.
5.3.9Internal SMBus Memory Register Set
The following table provides the SMBus slave interface register map values.
Table 5.4 SMBus Slave Interface Register Map
REG | R/W | REGISTER NAME | ABBR | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
ADDR | (MSB) | (LSB) | |||||||||
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00h | R/W | Status/Command | STCD | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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01h | R/W | VID LSB | VIDL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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02h | R/W | VID MSB | VIDM | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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03h | R/W | PID LSB | PIDL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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04h | R/W | PID MSB | PIDM | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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05h | R/W | DID LSB | DIDL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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06h | R/W | DID MSB | DIDM | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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07h | R/W | Config Data Byte 1 | CFG1 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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08h | R/W | Config Data Byte 2 | CFG2 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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09h | R/W | NRD | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
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0Ah | R/W | Port Disable (Self) | PDS | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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0Bh | R/W | Port Disable (Bus) | PDB | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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SMSC USB2504/USB2504A | 27 | Revision 2.3 |
| DATASHEET |
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