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Datasheet
Figure 8.3 HS Detection Handshake Timing Behavior (FS Mode)
Table 8.6 HS Detection Handshake Timing Values (FS Mode)
TIMING |
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PARAMETER | DESCRIPTION |
| VALUE |
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T0 | HS Handshake begins. DP | 0 (reference) | |
| terminations disabled. |
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T1 | Device enables HS Transceiver and asserts Chirp | T0 | < T1 < HS Reset T0 + 6.0ms |
| K on the bus. |
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T2 | Device removes Chirp K from the bus. 1ms | T1 | + 1.0 ms < T2 < |
| minimum width. | HS Reset T0 + 7.0ms | |
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T3 | Earliest time when downstream facing port may | T2 | < T3 < T2+100µs |
| assert Chirp KJ sequence on the bus. |
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T4 | Chirp not detected by the device. Device reverts to | T2 | + 1.0ms < T4 < |
| FS default state and waits for end of reset. | T2 | + 2.5ms |
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T5 | Earliest time at which host port may end reset | HS Reset T0 + 10ms | |
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Notes:
T0 may occur to 4ms after HS Reset T0.
The SIE must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration.
SMSC USB3290 | 33 | Revision 1.5 |
| DATASHEET |
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