High Speed Inter-Chip USB 2.0 Hub and Flash Media Controller

Datasheet

Chapter 7 Pin Reset States

HardwareFirmware

Initialization Operational

Voltage

Signal RESET

(v)

RESET

VDD33

VSS

Time

(t)

Figure 7.1 Pin Reset StatesTable 7.1 Legend for Pin Reset States Table

SYMBOL

DESCRIPTION

 

 

0

Output driven low

 

 

1

Output driven high

 

 

IP

Input enabled

 

 

PU

Hardware enables pull-up

 

 

PD

Hardware enables pull-down

 

 

none

Hardware disables pad

 

 

--

Hardware disables function

 

 

Z

Hardware disables pad. Both output

 

driver and input buffers are disabled.

 

 

7.1Pin Reset States

Table 7.2 USB4640/USB4640i Reset States Table

 

 

 

 

 

RESET STATE

 

 

 

 

 

 

 

 

 

 

 

PIN

 

PIN NAME

 

FUNCTION

 

INPUT/

PU/

 

 

 

 

OUTPUT

PD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

USBDN_DM2

 

USBDN_DM2

 

IP

PD

 

 

 

 

 

 

 

 

 

 

2

 

USBDN_DP2

 

USBDN_DP2

 

IP

PD

 

 

 

 

 

 

 

 

 

 

3

 

USBDN_DM3

 

USBDN_DM3

 

IP

PD

 

 

 

 

 

 

 

 

 

 

4

 

USBDN_DP3

 

USBDN_DP3

 

IP

PD

 

 

 

 

 

 

 

 

 

 

6

 

PRTCTL2

 

PRTCTL

 

0

--

 

 

 

 

 

 

 

 

 

 

7

 

PRTCTL3

 

PRTCTL

 

0

--

 

 

 

 

 

 

 

 

 

 

SMSC USB4640/USB4640i

25

Revision 1.0 (06-01-09)

DATASHEET