High Speed Inter-Chip USB 2.0 Hub and Flash Media Controller

Datasheet

8.4.6I2C EEPROM

The I2C EEPROM interface implements a subset of the I2C Master Specification (Please refer to the Philips Semiconductor Standard I2C-Bus Specification for details on I2C bus protocols). The device’s I2C EEPROM interface is designed to attach to a single “dedicated” I2C EEPROM, and it conforms to the Standard-mode I2C Specification (100 kbps transfer rate and 7-bit addressing) for protocol and electrical compatibility.

Note: Extensions to the I2C Specification are not supported. The device acts as the master and generates the serial clock SCL, controls the bus access (determines which device acts as the transmitter and which device acts as the receiver), and generates the START and STOP conditions.

8.4.6.1Implementation Characteristics

The device will only access an EEPROM using the sequential read protocol.

8.4.6.2Pull-Up Resistor

The circuit board designer is required to place external pull-up resistors (10 kΩ recommended) on the SPI_DO / GPIO5 / SDA / SPI_SPD_SEL and SPI_CLK / GPIO4 / SCL lines (per SMBus 1.0 Specification and EEPROM manufacturer guidelines) to VDD33 in order to assure proper operation.

8.4.7In-Circuit EEPROM Programming

The EEPROM can be programmed via automatic test equipment (ATE). Pulling nRESET low tri-states the device’s EEPROM interface and allows an external source to program the EEPROM.

8.5Default Configuration Option

The SMSC device can be configured via its internal default configuration. Please see Section 8.3.2, "EEPROM Data Descriptor" for specific details on how to enable default configuration. Please refer to Table 8.1 for the internal default values that are loaded when this option is selected.

8.6Reset

There are three different resets that the device experiences. One is a hardware reset from the internal power-on reset (POR) circuit, another reset is via the nRESET pin, and the third is a USB bus reset.

8.6.1Internal POR Hardware Reset

All reset timing parameters are guaranteed by design.

8.6.2External Hardware nRESET

A valid hardware reset is defined as assertion of nRESET for a minimum of 1 μs after all power supplies are within operating range. While reset is asserted, the device (and its associated external circuitry) consumes less than 500 μA of current.

Assertion of nRESET (external pin) causes the following:

1.All downstream ports are disabled and PRTCTL power to downstream devices is removed.

2.The PHYs are disabled and the differential pairs will be in a high-impedance state.

3.All transactions immediately terminate; no states are saved.

4.All internal registers return to the default state (in most cases, 00h).

5.The external crystal oscillator is halted.

Revision 1.0 (06-01-09)

52

SMSC USB4640/USB4640i

DATASHEET