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| User’s Manual | |
2.4.11.1 Signal Description – Primary IDE Connector (JIDE1) | |||
| Signal | Signal Description |
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| PDA [2:0] | IDE Address Bits. These address bits are used to access a register or data port in |
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| a device on the IDE bus. |
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| DCS1#, DCS3# | IDE Chip Selects. The chip select signals are used to select the command block |
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| registers in an IDE device. DCS1# selects the primary hard disk. |
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| PDD [15:0] | IDE Data Lines. D [15:0] transfers data to/from the IDE devices. |
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| PIOR# | IDE I/O Read. Signal is asserted on read accesses to the corresponding IDE port |
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| addresses. |
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| PIOW# | IDE I/O Write. Each signal is asserted on write accesses to corresponding the IDE |
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| port addresses. |
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| PIORDY | When deasserted, these signals extend the transfer cycle of any host register |
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| access when the device is not ready to respond to the data transfer request. |
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| RESET# | IDE Reset. This signal resets all the devices that are attached to the IDE |
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| interface. |
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| PIRQ14 | Interrupt line from hard disk. Connected directly to |
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| PDREQ | The DREQ is used to request a DMA transfer from the South Bridge. The |
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| direction of the transfers is determined by the IOR#/IOW# signals. |
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| PDACK# | DMA Acknowledge. The DACK# acknowledges the DREQ request to initiate DMA |
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| transfers. |
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| PDACT# | Signal from hard disk indicating hard disk activity. The signal level depends on the |
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| hard disk type, normally active low. The signal is routed directly to the LED1. |
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