• DIGITAL BOARD IC1401 CXD2712R (AUDIO DSP)
Pin No. |
| Pin Name | I/O |
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1 |
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| VSS3 | — | Ground terminal |
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2 to | 5 |
| SOA to SOD | O | Serial data output to the A/D, D/A converter |
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6, 7 |
| ECJ0, ECJ1 | I | Conditional jump input terminal (fixed at “L” in this set) |
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8 |
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| NC | O | Not used (fixed at “L”) |
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9 |
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| XHDWR | I | Write data input from the system controller (IC1201) |
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10 |
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| XHDRD | I | Read data input terminal Not used (fixed at “H”) |
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11 |
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| VSS4 | — | Ground terminal |
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12 |
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| VDD2 | — | Power supply terminal (+3.3V) |
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13 |
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| HRDY | O | Ready signal output to the system controller (IC1201) |
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14 |
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| XHDCS | I | Chip select signal input from the system controller (IC1201) | |||
15 |
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| HA0 | I | Address signal input from the system controller (IC1201) | |||
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16 to | 20 |
| HD0 to HD4 | I/O |
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21 |
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| VSS5 | — | Ground terminal |
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22 |
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| VDD3 | — | Power supply terminal (+3.3V) |
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23 to | 25 |
| HD5 to HD7 | I/O |
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26 |
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| XRST | I | Reset signal input from the system controller (IC1201) | “L”: reset | ||
27 to | 30 |
| FGP0 toFGP3 | I/O | Data output terminal for the test |
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31 |
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| VSS6 | — | Ground terminal |
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32 to | 40 |
| ED0 to ED8 | I/O | Not used (fixed at “L”) | |||
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41 |
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| VSS7 | — | Ground terminal |
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42 |
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| VDD4 | — | Power supply terminal (+3.3V) |
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43 to | 49 |
| ED9 to ED15 | I/O | Not used (fixed at “L”) | |||
50 |
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| TEST | I | Test terminal (Normally: fixed at “L”) |
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51 |
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| VSS8 | — | Ground terminal |
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52 |
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| VDD5 | — | Power supply terminal (+3.3V) |
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53 to | 60 | ED16 to ED23 | I/O |
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61 |
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| VSS9 | — | Ground terminal |
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62 to | 69 | ED24 to ED31 | I/O |
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70 |
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| XOE | O | Output enable signal output to the |
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71 |
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| VSS10 | — | Ground terminal |
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72 |
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| VDD6 | — | Power supply terminal (+3.3V) |
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73 |
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| CAS | O | External RAM column address strobe signal output terminal Not used | |||
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74 |
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| XWE | O | Write enable signal output to the |
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75 |
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| RAS | O | External RAM raw address strobe signal output terminal | Not used | ||
76 to | 80 |
| EA0 to EA4 | O | Address signal output to the | |||
81 |
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| VSS11 | — | Ground terminal |
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82 |
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| VDD7 | — | Power supply terminal (+3.3V) |
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83 to | 89 |
| E5 to EA11 | O | Address signal output to the | |||
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90 |
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| EA12 | O | Address signal output to the |
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91 |
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| VSS0 | — | Ground terminal |
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92 to | 94 | EA13 to EA15 | O | Address signal output to the |
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95 |
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| EA16 | O | Address signal output terminal (for check) |
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96 |
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| TSTA | I | Test data input terminal (Normally: fixed at “L”) |
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97 |
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| PLDIVF | I | PLL input frequency select terminal | “L”: 256fs “H”: 128fs (fixed at “L” in this set) | ||
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98 |
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| PLDIVB | O | PLL input frequency select terminal | “L”: 768fs “H”: 1024fs (fixed at “H” in this set) | ||
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51