BIOS Setup Utility
CHIPSET FEATURES SETUP (Continued)
| CHIPSET |
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| Setting | Description | Note |
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| FEATURES |
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DRAM CAS Select
Auto (By SPD)
2.5(DDR) / 3 (SDR) 2 (DDR) / 2 (SDR)
When synchronous 
DRAM is installed, the Default number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the system designer.
DARM Performance
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Auto (By SPD) | This item allow you to |
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Failsafe | control the DRAM timing. |
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Slow |
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Normal |
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Fast |
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Ultra |
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Ultra2 |
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AT Bus Clock
System BIOS Cacheable
7.16 MHz | This item allow you to |
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CLK2/2 | control the ISA Bus clock. |
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CLK2/3 |
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CLK2/4 |
| Default |
CLK2/5 |
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CLK2/6 |
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Disabled |
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Enabled | The ROM area |
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| cacheable. |
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