SOYO SY-K7ADA V1.0 user manual Chipset Features Setup

Models: SY-K7ADA V1.0

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BIOS Setup UtilitySY-K7ADA V1.0

CHIPSET FEATURES SETUP (Continued)

 

CHIPSET

 

 

Setting

Description

Note

 

 

 

 

 

 

FEATURES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRAM CAS Select

Auto (By SPD)

2.5(DDR) / 3 (SDR) 2 (DDR) / 2 (SDR)

When synchronous DRAM is installed, the Default number of clock cycles of

CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the system designer.

DARM Performance

 

 

 

Auto (By SPD)

This item allow you to

 

Failsafe

control the DRAM timing.

 

Slow

 

 

Normal

 

Default

Fast

 

 

Ultra

 

 

Ultra2

 

 

 

 

 

AT Bus Clock

System BIOS Cacheable

7.16 MHz

This item allow you to

 

CLK2/2

control the ISA Bus clock.

 

CLK2/3

 

 

CLK2/4

 

Default

CLK2/5

 

 

CLK2/6

 

 

 

 

 

Disabled

 

Default

Enabled

The ROM area

 

 

F0000H-FFFFFH is

 

 

cacheable.

 

 

 

 

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Page 64
Image 64
SOYO SY-K7ADA V1.0 user manual Chipset Features Setup