Motherboard Description | SY-K7ADA V1.0 |
1-7 CHIPSET
ALi M1647 Overview
The M1647 is a high performance, high value North Bridge that supports all Athlon family processors. Internally all 128-bit architecture with optimization for S2K bus, DDR and AGP4X interface, the M1647 has outstanding high system performance under all types of system operations. The M1647 North Bridge, coupled with one of ALi’s widely adopted PCI South Bridge devices (M1535D+) provides a flexible and scalable motherboard core logic solution to fill all applications.
The M1647 supports all Athlon family microprocessors. Processor bus speeds of 66MHz to 133MHz are supported. This interface has 16 entries for outstanding processor commands and system probe commands. This interface supports FID change protocol for mobile purposes.
The M1647 can support up to 3.0 GB of SDRAM or DDR-SDRAM main memory. Supports any combination of 66/100/133MHz memory bus frequency and CPU bus frequency with minimized internal protocol handshaking overhead, the M1647 provides a flexible system application. In addition to dynamic memory power down, the M1647 also supports a dynamic gated clock for the internal chipset logic circuitry, which will reduce the system power consumption for mobile applications. The m1647 support the CAS-before-RAS refresh scheme and Self-refresh scheme during normal mod and suspend mode, respectively.
The memory access controller plays a key role of dispatching the job to the memory interface. By using a two-level dynamic arbitration scheme, the M1647 fulfills multiple demanding sources that need access to the main memory with balanced latency and maximum throughput. Another important role of the memory access controller is the integration logic between the AGP interface and main memory to support the AGP memory address to physical memory address translate. To fulfill this function, the M1647 uses 128 entries and 16 tags to implement a one level GART (Graphic Address Re-mapping Table) scheme.
The M1647 supports all features of the AGP version 2.0 specification. This
