PIN CONFIGURATION
8-Pin PDIP
or 8-Pin SOIC
CS | | | 1 | 8 | | VCC |
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SK | | | | | 2 | 7 | | RESET |
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DI | | | | 3 | 6 | | RESET# |
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DO | | | | 4 | 5 | | GND |
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2029 T PCon 2.0
PIN FUNCTIONS
Pin Name | Function |
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CS | Chip Select |
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SK | Clock Input |
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DI | Serial Data Input |
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DO | Serial Data Output |
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VCC | +2.7 to 6.0V Power Supply |
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GND | Ground |
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RESET/RESET# | RESET I/O |
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DEVICE OPERATION
APPLICATIONS
The S93WD462/WD463 is ideal for applications requir- ing low voltage and low power consumption. This device provides microcontroller RESET control and can be manually resettable.
RESET CONTROLLER DESCRIPTION
The S93WD462/WD463 provides a precision reset con- troller that ensures correct system operation during brownout and power-up/-down conditions. It is config- ured with two open drain reset outputs; pin 7 is an active high output and pin 6 is an active low output.
During power-up, the reset outputs remain active until
VCC reaches the VTRIP threshold. The outputs will con- tinue to be driven for approximately 150ms after reaching
VTRIP. The reset outputs will be valid so long as VCC is ≥ 1.0V. During power-down, the reset outputs will begin driving active when VCC falls below VTRIP.
The reset pins are I/Os; therefore, the S93WD462/ WD463 can act as a signal conditioning circuit for an
externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset time-out after detecting a low to high transition and the RESET# input will initiate a reset time-out after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a debounce/ reset extender circuit.
It should be noted the reset outputs are open drain. When used as outputs driving a circuit they need to be either tied high (RESET#) or tied to ground (RESET) through the use of pull-up or pull-down resistors. Refer to the applications aid section for help in determining the value of resistor to be used. Internally these pins are weakly pulled up (RESET#) and pulled down (RESET): there- fore, if the signals are not being used the pins may be left unconnected.
WATCHDOG TIMER DESCRIPTION
The S93WD462/WD463 has a watchdog timer with a nominal time-out period of 1.6 seconds. Whenever the
watchdog times out, it will generate a reset output to both pins 6 and 7. The watchdog timer is reset by any transition on CS.
The watchdog timer will be held in a reset state during power-on while VCC is less than VTRIP. Once VCC exceeds VTRIP the watchdog will continue to be held in a reset state for the tPURST period. After tPURST it will be released and the timer will begin operation. If either reset input is asserted the watchdog timer will be reset and remain in the reset condition until either tPURST has expired or the reset input is released, whichever is longer.
GENERAL OPERATION
The S93WD462/WD463 is a 1024-bit nonvolatile memory intended for use with industry standard microproces- sors. The S93WD463 is organized as X16, seven 9-bit instructions control the reading, writing and erase operations of the device. The S93WD462 is organized as X8, seven 10-bit instructions control the reading, writing and erase operations of the device. The device operates on a single 3V or 5V supply and will generate on chip, the high voltage required during any write opera- tion.
