Sun Microsystems T5220, T5120 manual Integrated Networking, Stream Processing Unit

17 The UltraSPARC T2 Processor with CoolThreads Technology Sun Microsystems, Inc.

Integrated Networking

By providing integrated on-chip networking, the UltraSPARC T2 processor is able to provide better networking performance. All network data is supplied directly from and to main memory. Placing networking so close to memory reduces latency, provides higher memory bandwidth, and eliminates inherent inefficiencies of I/O protocol translation.

The UltraSPARC T2 processor provides two 10 Gb Ethernet ports with integrated serdes, offering line-rate packet classification at up to 30 million packets/second (based on layers 1-4 of the protocol stack). Multiple DMA engines (16 transmit and 16 receive DMA channels) match DMAs to individual threads, providing binding flexibility between ports and threads. Virtualization support includes provisions for eight partitions, and interrupts may be bound to different hardware threads.

Stream Processing Unit

The stream processing unit on each UltraSPARC T2 core runs in parallel with the core at the same frequency. Two independent sub-units are provided along with a DMA engine that shares the core’s crossbar port:

•A Modular Arithmetic Unit (MAU) shares the FGU multiplier, providing RSA encryption/decryption, binary and integer polynomial functions, as well as elliptic curve cryptography (ECC)1

•The cipher/hash unit provides support for popular RC4, DES/3DES, AES-128/192/256, MD5, SHA-1, and SHA-256 ciphers

The SPU is designed to achieve wire-speed encryption and decryption on both of the processor’s 10 GB Ethernet ports.

Integral PCI Express Support

The UltraSPARC T2 processor provides an on-chip PCI Express interface that operates at 4 GB/second bidirectionally through a point-to-point dual-simplex chip interconnect. An integral IOMMU supports I/O virtualization and process device isolation by using the PCI Express BDF number. The total I/O bandwidth is 3-4 GB/second, with maximum payload sizes of 128 to 512 bytes. An x8 serdes interface is provided for integration with off-chip PCI Express switches.

1.Supported in a future Solaris OS release