Appendix D: Performance Verification
73A-270 Arbitrary Pulse/Pattern Generator Module 65
Table A–5: Pulse Duration Multiplier Verification
Command to Send Multiplier /
Resolution Verify Period and
Duty Cycle
IBWRT "0A0R10001L10004L0C0B"
(step 3 repeated for table continuity) 1000 100 ns 5 kHz ±0.5 Hz, 50%
±0.1%
IBWRT "1R0A1001L1004L0C0B" 100 1 ms5 kHz ±0.5 Hz, 50%
±0.1%
IBWRT "2R0A101L104L0C0B" 10 10 ms5 kHz ±0.5 Hz, 50%
±0.1%
IBWRT "3R0A11L14L0C0B" 1 100 ms5 kHz ±0.5 Hz, 50%
±0.1%
IBWRT "0A21L24L" 2 100 ms2.5 kHz ±0.25 Hz, 50%
IBWRT "0R0A8585851L4242424L0C0B" 858585 high,
424242 low 85.8585 ms ±20 ns,
42.4242 ms ±20 ns
5. Verify the pulse-pattern burst count function with the following steps:
a. Connect the TTL OUT A or (TTL OUT B) to the counter/timer
INPUT B input.
b. Set the 73A-270 for a 10 ms resolution, to first address location, to
retriggerable mode, for a first List entry of 550 ms active high, and for a
second list entry of 550 ms active low and designated as the Last
Address.
IBWRT "Q"
IBWRT "2R0A0M551L554L"
c. Set the counter/timer for Basic Timer/Counter Measurement Mode, to
Function Event Count B, for a Ch-B Trigger at 1 V, to Gate Indefinitely,
and to return an Integer Format of maximum 217–1 value.
IBFIND VX541
IBWRT "ER"
(Query for any pending ERROR conditions)
IBRD 100
(Observe a 99 response; no ERRORs)
IBWRT "MM0;FN4;BT+100;BZ1;GI;IF17"
IBWRT "JM"
(Start the counter/timer measurement cycle)
d. Set the 73A-270 to generate the pulse-pattern List 42 times and to begin.