5 ADC Evaluation5.1 Hardware Selection
5.1.1 Analog Input Signal Generator
5.1.2 Clock Signal Generator
ADC Evaluation
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This section describes how to set up a typical ADC evaluation system that is similar to what TI uses toperform testing for data-sheet generation. Consequently, the information in this section is generic in natureand is applicable to all high-speed, high-resolution ADC evaluations. This section covers signal toneanalysis, which yields ADC data-sheet figures of merit such as signal-to-noise ratio (SNR) and spuriousfree dynamic range (SFDR).
To reveal the true performance of the ADC under evaluation, great care should be taken in selecting boththe ADC signal source and ADC clocking source.
When choosing the quality of the ADC analog input source, consider both harmonic distortion performanceof the signal generator and the noise performance of the source.
In many cases, the harmonic distortion performance of the signal generator is inferior to that of the ADC,and additional filtering is needed if users expect to reproduce the ADC SFDR numbers found in the datasheet. Users can easily evaluate the harmonic distortion of the signal generator by hooking it directly to aspectrum analyzer, measuring the power of the output signal, and comparing that to the power of theinteger multiples of the output signal frequency. If the harmonic distortion is worse than the ADC underevaluation, the ADC digitizes the performance of the signal generator and the true SFDR of the ADC ismasked. To alleviate this, it is recommended that users provide additional LC filtering after the signalgenerator output.
Another important metric when deciding on a signal generator is its noise performance. As with thedistortion performance, if the noise performance is worse than that of the ADC under evaluation, the ADCdigitizes the performance of the source. Noise can be broken into two components, broadband noise andclose-in phase noise. Broadband noise can be improved by the LC filter added to improve distortionperformance; however, the close-in phase noise typically cannot be improved by additional filtering.Therefore, when selecting an analog signal source, it is important to review the manufacturer's phasenoise plots and take care to choose a signal generator with the best phase-noise performance.
Equally important in the high-performance ADC evaluation setup is the selection of the clocking source.Most modern ADCs, the ADS61xx/ADS61B23 included, accept either a sinusoidal or a square-wave clockinput. The key metric in selecting a clocking source is selecting a source with the lowest jitter. Thisbecomes increasingly important as the ADC input frequency (f
in
) increases, because the ADC SNRevaluation setups can become jitter-limited (t
j
) as shown by the following equation.
SNR (dBc) = 20 log (2 π×f
in
×t
j
(rms))
In theory, a square-wave source with femtosecond jitter would be ideal for an ADC evaluation setup.However, in practical terms, most commercially available square-wave generators offer jitter measured inpicoseconds, which is too great for high-resolution ADC evaluation setups. Therefore, most evaluationsetups rely on the ADC internal clock buffer to convert a sinusoidal input signal into a ultralow-jitter squarewave. When selecting a sinusoidal clocking source, it has been shown that phase noise has a directimpact on jitter performance. Consequently, great scrutiny should be applied to the phase-noiseperformance of the clocking signal generator. TI has found that high-Q monolithic crystal filters canimprove the phase noise of the signal generator, and these filters become essential elements of theevaluation setup when high ADC input frequencies are being evaluated.
14 SLAU206B – September 2007 – Revised April 2008Submit Documentation Feedback