2.2.4 ADC Clock Input
2.2.5 ADC Digital Outputs
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Circuit Description
Note that the THS4509 used on this EVM is pinout compatible with the THS4508 ,THS4511 ,THS4513 ,and THS4520 . Users can easily interchange the amplifier on this EVM and pick the appropriate amplifierbased on common-mode range, power supplies, and frequency of operation. Contact your local TexasInstruments (TI) sales representative for assistance in selection of these amplifiers.
Connect a filtered, low-phase-noise clock input to J9. A transformer, T3, provides the conversion from asingle-ended clock signal into a differential clock signal.
The EVM also provides a clock distribution path using the CDCP1803. The CDCP1803 provides for a 1:3LVDS fanout helpful when clocking multiple ADCs from the same clocking source. Users selecting thisinput path should use a low-jitter square-wave input. In addition, the CDCP1803 jitter performance makesthis a valid clocking solution only for input frequencies in the first Nyquist zone, as jitter degrades SNR forfrequencies much above the first Nyquist zone. To use this path, change jumper JP8 to short 1–2, andJP2, JP3, and JP4 to short pins 2–3.
The ADS61xx/ADS61B23 ADC parallel digital outputs are brought to J10, a high-density Samtec™connector. Several options are available in processing the ADC data.
1. The mating logic analyzer breakout board can capture the ADC data using a logic analyzer. Users whochoose this option should use the companion breakout board and Table 1 for the connection details.Users lacking access to a logic analyzer can use the TSW1100 to capture the digital data. See theconnection guidelines in Section 4.1 .
2. Users can create their own digital interface board which directly interfaces to the ADC. In this case,they design their mating digital interface board with the Samtec part number QSO-060-01-F-D-A, whichis the companion part number to the EVM connector.
SLAU206B – September 2007 – Revised April 2008 7Submit Documentation Feedback