Texas Instruments TAS5066PAG Loudspeaker Connectors J100 − J600, 5. J100− J600 Pin Description

Models: TAS5066PAG

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Both positive and negative speaker outputs are floating and may not be connected to ground (e.g., through an oscilloscope).

Figure 2−4. J100 − J600 Pin Numbers (PCB Connector Top View)

System Interfaces

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Contents

TAS5066-5111D6EVM PurePath DigitalE EVM User’s GuideMarch Digital Audio and Video ProductsApplications IMPORTANT NOTICEProducts EVM IMPORTANT NOTICE EVM WARNINGS AND RESTRICTIONS Read This First How to Use This ManualAbout This Manual Information about Cautions and WarningsAdditional Documentation Related Documentation from Texas InstrumentsFCC Warning TrademarksContents Tables FiguresChapter OverviewPage TopicTAS5066-5111D6EVMFeatures 1.1TAS5066-5111D6EVMFeaturesFigure 1−1. Complete PurePath Digital E System Overview 1.2 PCB Key MapPCB Key Map Page Chapter System InterfacesPage Topic2.1 PSU Interface J901 Table 2−1. Recommended Power SuppliesFigure 2−1. Recommended Power-UpSequence Table 2−3. J903 Pin Description Table 2−2. J901 Pin DescriptionNet-Nameat Schematics Net-Nameat SchematicsPSU Control Interface J902 2.2 PSU Control Interface J902Table 2−4. J902 Pin Description Table 2−5. J100− J600 Pin Description 2.3 Loudspeaker Connectors J100 − J600Loudspeaker Connectors J100 − J600 System InterfacesControl Interface J50 2.4 Control Interface J50Table 2−6. J50 Pin Description Table 2−7. J51 Pin Description 2.5 Digital Audio Interface J51Table 2−8. Clock Rates Digital Audio Interface J51PWM Timing, Interchannel Delay Registers 2.6 PWM Timing, Interchannel Delay RegistersRegister Description RegisterDevice Fault Reporting ProtectionChapter PageTable 3−1. TAS5111 Error Signal Decoding 3.2 Device Fault Reporting