Manuals / Texas Instruments / Home Audio / Stereo Amplifier

Texas Instruments TAS5066PAG manual PWM Timing, Interchannel Delay Registers, Register Description

Models: TAS5066PAG

1 22

Download 22 pages 24.22 Kb

Page 20

Image 20

PWM Timing, Interchannel Delay Registers

2.6 PWM Timing, Interchannel Delay Registers

For maximum performance, the PWM timing must be optimized for the specific configuration and PCB layout. The default values in TAS5066 is properly not optimal in many designs and therefore the interchannel delays must be pro- grammed by I2C to the TAS5066 at startup and after every system reset.

Table 2−9. Recommended Interchannel Delay Register Values (based on EVM designs)

Register Description	Register	Value (hex)
	Address

Inter−Channel Delay Channel 1	0x0C	0x01

Inter−Channel Delay Channel 2	0x0D	0x49

Inter−Channel Delay Channel 3	0x0E	0x91

Inter−Channel Delay Channel 4	0x0F	0xD9

Inter−Channel Delay Channel 5	0x10	0x21

Inter−Channel Delay Channel 6	0x11	0x69

2-8

Page 20

Image 20

Texas Instruments TAS5066PAG manual PWM Timing, Interchannel Delay Registers, Register Description, Value hex, Address

Contents

User’s Guide TAS5066-5111D6EVM PurePath DigitalE EVMMarch Digital Audio and Video ProductsApplications IMPORTANT NOTICEProducts EVM IMPORTANT NOTICE EVM WARNINGS AND RESTRICTIONS How to Use This Manual Read This FirstAbout This Manual Information about Cautions and WarningsRelated Documentation from Texas Instruments Additional DocumentationFCC Warning TrademarksContents Figures TablesOverview ChapterPage TopicTAS5066-5111D6EVMFeatures 1.1TAS5066-5111D6EVMFeaturesFigure 1−1. Complete PurePath Digital E System Overview 1.2 PCB Key MapPCB Key Map Page System Interfaces ChapterPage Topic2.1 PSU Interface J901 Table 2−1. Recommended Power SuppliesFigure 2−1. Recommended Power-UpSequence Table 2−2. J901 Pin Description Table 2−3. J903 Pin DescriptionNet-Nameat Schematics Net-Nameat SchematicsPSU Control Interface J902 2.2 PSU Control Interface J902Table 2−4. J902 Pin Description 2.3 Loudspeaker Connectors J100 − J600 Table 2−5. J100− J600 Pin DescriptionLoudspeaker Connectors J100 − J600 System InterfacesControl Interface J50 2.4 Control Interface J50Table 2−6. J50 Pin Description 2.5 Digital Audio Interface J51 Table 2−7. J51 Pin DescriptionTable 2−8. Clock Rates Digital Audio Interface J512.6 PWM Timing, Interchannel Delay Registers PWM Timing, Interchannel Delay RegistersRegister Description RegisterProtection Device Fault ReportingChapter Page3.2 Device Fault Reporting Table 3−1. TAS5111 Error Signal Decoding

PWM Timing, Interchannel Delay Registers

2.6 PWM Timing, Interchannel Delay Registers

Register Description

Register

Value (hex)

Address