Application Report
SLLA032
Designator | Function | Condition (TNETE2201) |
| | |
DIP1-4 | LCKREFN | X (OFF) |
DIP1-5 | TESTEN | ON |
DIP1-6 | SYNCEN | X (OFF) |
DIP1-7 | LOOPEN | ON |
DIP1-8 | CLKEN | X (OFF) |
Note: X is a don't care state (default position).
The GBIC Configuration requires a modification of the steering capacitors C23 through C30. This requires removing C24, C26, C27, and C30 and soldering these capacitors in locations C23, C25, C28, and C29 (see Figure 1).
Figure 1. GBIC Setup Modifications
GBIC
INSTALLED
CAPACITORS
Test Configuration and Results
The serial Bit Error-rate Ratio Test (BERT) is useful for evaluating device and board characteristics. Using this test, we can determine the eye diagram characteristics of the system, as shown in Figure 3. The test setup is illustrated in Figure 2.
The HP71603B 3-Gbps Serial BERT outputs a high-speed serial stream to the test board where the data is converted by the TNETE part to a 10-bit parallel format. The parallel data is then looped back from the receiver to the transmitter. The pulse generator provides a clock input to the transmitter. The external clock source is necessary because the receiver's recovered clock is half the frequency necessary for transmission.
TNETE2201 EVM Kit Setup and Usage | 4 |
