9
Circuit Description
Control Circuit
Major frequency control functions such as channel
selection, display, and PLL divider control are per-
formed by main CPU Q1018 (HD64F2134) on the
MAIN Unit, at the command of the user via the tun-
ing knob and function switches on the front panel.
The programmable divider data for the PLL from
the main CPU is applied directly to DDS IC Q1016
(AD9833BRM) and PLL subsystem IC Q1056
(ADF4001BRU).
The Mode selection data from the main CPU is also
delivered to DSP IC Q1035 (UPD77115) to control
the various circuits required for the selected mode.
The Band selection binary data from the main CPU
is decoded (BCD to Decimal) by Q1011 (TC4028BF).
The resulting decimal outputs are level-shifted by
Q1003 (TD62783AF) to select the active band-pass
filter on the MAIN Unit required for the operating
frequency. Also, the decimal outputs from Q1003
(TD62783AF) are delivered to PA Unit, where they
are used to select the active low-pass filter required
for the operating frequency.
TX/RX Control
When the PTT switch is pressed, pin 21 of the main
CPU Q1018 (HD64F2134) goes low, which causes
pin 60 of the main CPU Q1018 (HD64F2134) to go
low. This signal disables the receiver 12 V bus at
Q1046 (2SA1602A). At the same time, pin 59 of the
main CPU Q1018 (HD64F2134) goes low to activate
the transmit 12 V bus at Q1048 (2SA1365).
Power Supply & Regulation
The +5 V bus for the main CPU Q1018 (HD64F2134)
is derived from the 13.5 V bus via regulator Q1012
(BA05FP) on the MAIN Unit. The +8 V bus is de-
rived from the 13.5 V bus via regulator Q1007
(KIA7808API) on the MAIN Unit.
A portion of the +8 V bus is regulated by Q1008
(L78M05T) for the +5 V bus, and is regulated by
Q1006 (UPC2926) for the +2.6 V bus required by the
DSP IC Q1035 (UPD77115GK).