ENGESBRA Distribuidor Autorizado Vertex Standard
Circuit Description
The modulated signal from the VCO Q1054 (2SK508) is buff- ered by Q1049 (2SC5226) and amplified by Q1038 and Q1002 (both 2SC5226). The
The output power of Power Module is detected by CM coupler, it is detected by D1013 and D1014 (both HSM88AS) and is input to comparator Q1090 (NJM12902V). The comparetor compares two different voltages and makes output power stable by controlling the bias voltage of Power Module. There are 3 levels of output power (Hi, Mid and Lo), it is switched by the voltage of
The frequency synthesizer consists of PLL IC Q1085 (SK7025DK), Q1045 (DTC114TE), VCO, TCXO (X1003) and buffer amplifier. The output frequency from TCXO is 16.8 MHz and the tolerance is ±2.5 ppm (in the temperature range
While the radio is receiving, the RX oscillator Q1054 (2SK508) in VCO generates a programmed frequency between 184.85 and
224.85MHz as 1st local signal. While the radio is transmitting, the TX oscillator Q1058 (2SC3356) in VCO generates a fre- quency between 134 and 174 MHz. The output from oscillator is amplified by buffer amplifier Q1049 (2SC5226) and becomes output of VCO. The output from VCO is divided, one is ampli- fied by Q1057 (2SC5226) and feed back to pin 5 of the PLL IC Q1085 (SK7025DK). The other is amplified in Q1038 (2SC5226) and in case of the reception, it is put into the mixer as the 1st local signal through D1022 (DA221), in transmis- sion, it is amplified in Q1038 (2SC5226), and more amplified in Q1002 (2SC5226) through D1022 (DA221) and it is put the input terminal of the Power Module Q1028
Tuning voltage (VCV) of VCO is expanding the lock range of VCO by controlling the anode of varactor diode at the negative voltage and the control voltage from PLL IC Q1085 (SK7025DK). The negative voltage is added to the varactor diode after converted to negative by Q1035 (SPM5001), which is output voltage of D/A converter Q1029 (M62364FP).
The PLL IC Q1085 (SK7025DK) consists of reference divider, main divider, phase detector, charge pumps and fractional accu- mulator. The reference frequency from TCXO is inputted to pin 8 of PLL IC Q1085 (SK7025DK) and is divided by reference divider. This IC is decimal point dividing PLL IC Q1085 (SK7025DK) and the dividing ratio becomes 1/8 of usual PLL frequency step. Therefore, the output of reference divider is 8 times of frequencies of the channel step. For example, when the channel stepping is 5 kHz, the output of reference divider be- comes 40 kHz. The other hand, inputted feed back signal to pin 5 of PLL IC Q1085 (SK7025DK) from VCO is divided with the dividing ratio which becomes same frequency as the output of reference divider. These two signals are compared by phase detector, the phase difference pulse is generated. The phase dif- ference pulse and the pulse from fractional accumulator pass through the charge pumps and LPF. It becomes the DC voltage (VCV) to control the VCO. The oscillation frequency of VCO is locked by the control of this DC voltage. The PLL serial data from CPU Q1083 (LC87F74C8A) is sent with three lines of SDO (pin 2), SCK (pin 1) and PSTB (pin 3). The lock condition of PLL is output from the UL (pin 18) terminal and UL becomes “H” at the time of the lock condition and becomes “L” at the time of the unlocked condition. The CPU Q1083 (LC87F74C8A) always watches over the UL condition, and when it becomes “L” unlocked condition, the CPU Q1083 (LC87F74C8A) prohibits transmitting and receiving.
ENGESBRA Distribuidor Autorizado Vertex Standard www.engesbra.com.br/vertex Tel.(11)
