PCI32 Interface v3.0
Fact Table Notes
1.Resource utilization depends on configuration of the interface and user design. Unused resources are trimmed by the Xilinx technology mapper. The utilization figures reported in this table are representative of a maximum configuration.
2.Designs running at 66 MHz in devices other than
3.See the PCI Getting Started Guide or product release notes for current supported versions.
4.XST is a command line option only. See the PCI Getting Started Guide for details.
5.Universal card implementations require two bitstreams.
6.Virtex and
7.Commercial devices: 0oC < Tj < 85oC.
Table 1: Core Implementation
Supported Device |
| Power Supply | |
|
|
|
|
|
| PCI32/66 | |
|
|
|
|
Virtex™ |
|
| 3.3V only |
|
|
|
|
|
| 3.3V only | |
|
|
|
|
|
| 3.3V only | |
|
|
|
|
(6,7) |
| 3.3V only | |
(regional clock based) |
|
| |
|
|
| |
|
|
|
|
(6,7) |
| 3.3V only | |
(regional clock based) |
|
| |
|
|
| |
|
|
|
|
(6,7) |
| 3.3V only | |
(regional clock based) |
|
| |
|
|
| |
|
|
|
|
|
| PCI32/33 | |
|
|
|
|
Virtex |
|
| 3.3V, 5.0V only |
|
|
|
|
Virtex |
|
| 3.3V, 5.0V only |
|
|
|
|
|
| 3.3V only | |
|
|
|
|
|
| 3.3V only | |
|
|
|
|
|
| 3.3V only | |
|
|
| |
| 3.3V only | ||
|
|
|
|
|
| 3.3V only | |
|
|
|
|
(6,7) |
| 3.3V only | |
(regional clock based) |
|
| |
|
|
| |
|
|
| |
| 3.3V only | ||
(regional clock based) |
|
| |
|
|
| |
|
|
|
|
(6,7) |
| 3.3V only | |
(regional clock based) |
|
| |
|
|
| |
|
|
|
|
(6,7) |
| 3.3V only | |
(global clock based) |
|
| |
|
|
| |
|
|
|
|
(6,7) |
| 3.3V only | |
(global clock based) |
|
| |
|
|
| |
|
|
|
|
(6,7) |
| 3.3V only | |
(global clock based) |
|
| |
|
|
| |
|
|
|
|
2 | www.xilinx.com | DS206 August 31, 2005 |
|
| Product Specification v3.0.151 |
