YMF744B
February 3, 1999
-53-

4. AC Characteristics

4-1. Master Clock (Fig.1)
Item Symbol Min. Typ. Max. Unit
XI24 Cycle Time tXICYC - 40.69 - ns
XI24 High Time tXIHIGH 13 - 24 ns
XI24 Low Time tXILOW 13 - 24 ns
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V
t

XI24

XICYC
t
XIHIGH
1.0 V
1.65 V
2.3 V
t
XILOW
Fig.1: XI24 Master Clock timing
4-2. Reset (Fig.2)
Item Symbol Min. Typ. Max. Unit
Reset Active Time after Power Stable tRST 1--ms
Power Stable to Reset Rising Edge tRSTOFF 10 - - ms
Reset Slew Rate - 50 - - mV/ns
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF

RST#

PVDD, LVDD,

VDD, CVDD

3.0 V
0.8 V

t

RST

t

RSTOFF
Fig.2: PCI Reset timing