Yamaha YMF744B (DS-1S) specifications PCI Interface, PCI Clock timing

YMF744B

4-3. PCI Interface (Fig.3,	4)
Item		Symbol	Condition	Min.	Typ.	Max.	Unit
PCICLK Cycle Time		tPCYC		30	-	-	ns
PCICLK High Time		tPHIGH		11	-	-	ns
PCICLK Low Time		tPLOW		11	-	-	ns
PCICLK Slew Rate		-		1	-	4	V/ns
PCICLK to Signal Valid Delay		tPVAL	(Bused signal)	2	-	11	ns
		tPVAL(PTP)	(Point to Point)	2	-	12	ns
Float to Active Delay		tPON		2	-	-	ns
Active to Float Delay		tPOFF		-	-	28	ns
		tPSU	(Bused signal)	7	-	-	ns
Input Setup Time to PCICLK		tPSU(PTP)	*11 (Point to Point)	10	-	-	ns
			*12 (Point to Point)	12	-	-	ns
Input Hold Time for PCICLK		tPH		0	-	-	ns

Note : Top = 0-70°C, PVDD=3.3 ±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, CL=10 pF *11: This characteristic is applicable to REQ# and PCREQ# signal.

*12: This characteristic is applicable to GNT# and PCGNT# signal.

		0.5 VDD3
PCICLK				0.4 VDD3
				0.3 VDD3
t PHIGH		t PLOW

t PCYC

PCICLK

OUTPUT

Tri-State

OUTPUT

Fig.3: PCI Clock timing

1.5 V

tPVAL

1.5 V

tPON

		t PSU	t PH
t
	POFF

INPUT 1.5 V

Fig.4: PCI Bus Signals timing

February 3, 1999

-54-