YMF744B
February 3, 1999
-56-
4-5. AC-link (Fig.6)
Item Symbol Condition Min. Typ. Max. Unit
CBCLK Cycle T ime tCBICYC - 81.4 - ns
CBCLK High Time tCBIHIGH 35 40.7 45 ns
CBCLK Low T i me tCBILOW 35 40.7 45 ns
CSYNC Cycle Time tCSYCYC - 20.8 - ns
CSYNC High Time tCSYHIGH -1.3-µs
CSYNC Low Time tCSYLOW - 19.5 - µs
CBCLK to Signal Valid Delay tCVAL *13 - - 20 ns
Output Hold Time for CBCLK tCOH *13 0 - - ns
Input Setup Time to CB CLK tCISU *14 15 - - ns
Input Hold T ime for CBCLK tCIH *14 5 - - ns
Warm Reset Width - 1.3 - µs
Note) Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF
*13: This characteristic is applicab le to CSYNC and CSDO signal.
*14: This characteristic is applicable to CSDI signal.
CBCLK
SYNC
CSDI
CSDO
0.8 V
1.5 V
2.0 V
0.8 V
2.0 V
0.8 V
2.0 V
0.8 V
1.5 V
2.0 V
t
CBIHIGH
t
CVAL
t
CBILOW
t
CBICYC
t
CVAL
t
COH
t
CSYCYC
t
CSYHIGH
t
COH
t
CSYLOW
t
CISU
t
CIH
Fig.6: AC-link timing