Intel manual Tables, SA-1100 Power and Clock Supply Sources and States

11-24	HP-SIR Modulation Example	11-104
11-25	UART Frame Format for IrDA Transmission (<= 115.2 Kbps)	11-105
11-26	4PPM Modulation Encodings	11-105
11-27	4PPM Modulation Example	11-106
11-28	High-Speed Serial Frame Format for IrDA Transmission (4.0 Mbps)	11-106
11-29	Example UART Data Frame	11-128
11-30	NRZ Bit Encoding Example – (0100 1011)	11-129
11-31	MCP Frame Data Format	11-147
11-32	MCP Frame Pin Timing	11-147
11-33	MPC/Codec Sampling Counter Synchronization	11-148
11-34	Audio/Telecom Transmit/Receive FIFO Data Format	11-150
11-35	Texas Instruments* Synchronous Serial Frame Format	11-170
11-36	Motorola* SPI Frame Format	11-171
11-37	National Microwire* Frame Format	11-172
11-38	Transmit/Receive FIFO Data Format	11-173
11-39	Motorola* SPI Frame Formats for SPO and SPH Programming	11-178
13-1	Memory Bus AC Timing Definitions	13-2
13-2	LCD AC Timing Definitions	13-3
13-3	MCP AC Timing Definitions	13-3
14-1	Quad Flat Pack – 1.4mm (LQFP)	14-1
14-2	SA-1100 256 Mini-Ball Grid Array Mechanical Drawing	14-3
16-1	Test Access Port (TAP) Controller State Transitions	16-1
16-2	Boundary-Scan Block Diagram	16-5
16-3	Boundary-Scan General Timing	16-7
16-4	Boundary-Scan Tristate Timing	16-8
16-5	Boundary-Scan Reset Timing	16-8
Tables
1-1	Features of the SA-1100 CPU for AA and EA Parts	1-2
1-2	Features of the SA-1100 CPU for CA and DA Parts	1-2
1-3	Changes to the SA-1100 Core from the SA-110	1-3
1-4	Additional Features Built into SA-1100 Chipset	1-3
2-1	Signal Descriptions	2-4
3-1	Vector Summary	3-4
4-1	Instruction Timings	4-1
5-1	Cache and MMU Control Registers (Coprocessor 15)	5-2
6-1	Effects of the Cacheable and Bufferable Bits on the Data Caches	6-3
7-1	Valid MMU, Dcache, and Write Buffer Combinations	7-2
8-1	Core Clock Configurations	8-2
9-1	OS Timer Register Locations	9-25
9-2	SA-1100 Power and Clock Supply Sources and States
	During Power-Down Modes	9-31
9-3	Pin State During Step	9-32
9-4	Power Manager Register Locations	9-40
9-5	Reset Controller Register Locations	9-43
10-1	SA-1100 Transactions	10-5
10-2	Memory Interface Control Registers	10-6
10-3	BS_xx Bit Encoding	10-13
10-4	BCLK Speeds for 160-MHz Processor Core Frequency	10-13

xviii SA-1100 Developer’s Manual