Intel SA-1100 manual OS Timer Status Register Ossr

System Control Module

9.4.4OS Timer Status Register (OSSR)

This status register contains status bits indicating whether a match has occurred on any of the four match registers. These bits are set when the event occurs (following the rising edge of the

3.6864-MHz clock) and cleared by writing a one to the proper bit position. Writing zeros to this register has no effect. All reserved bits read as zeros and are unaffected by writes; a question mark indicates that the value is unknown at reset.

Bit	31	30		29	28	27	26	25	24	23	22	21	20	19	18	17	16
R/W									Reserved
Reset	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0
Bit	15	14		13	12	11	10	9	8	7	6	5	4	3	2	1	0
R/W							Reserved							M3	M2	M1	M0
Reset	0	0		0	0	0	0	0	0	0	0	0	0	?	?	?	?
Bit	Name									Description
0	M0		Match status channel 0.
			0	– OS timer match register<0> has not matched the OS timer counter since the last
			clear.
			1	– OS timer match register<0> has matched the OS timer counter.
1	M1		Match status channel 1.
			0	– OS timer match register<1> has not matched the OS timer counter since the last
			clear.
			1	– OS timer match register<1> has matched the OS timer counter.
2	M2		Match status channel 2.
			0	– OS timer match register<2> has not matched the OS timer counter since the last
			clear.
			1	– OS timer match register<2> has matched the OS timer counter.
3	M3		Match status channel 3.
			0	– OS timer match register<3> has not matched the OS timer counter since the last
			clear.
			1	– OS timer match register<3> has matched the OS timer counter.
31..4	—		Reserved.

SA-1100 Developer’s Manual 9-23