Developer’s Manual
Intel StrongARM SA-1100 Microprocessor
SA-1100 Developer’s Manual
Contents
Memory-Management Unit MMU
Caches, Write Buffer, and Read Buffer
System Control Module
1.6
Memory and Pcmcia Control Module
Reviving the DRAMs from Self-Refresh Mode
Peripheral Control Module
11-39
11.8.3.4Endpoint 0 Interrupt Mask EIM 11-64 11.8.3.5Receive
11-81
SA-1100 Developer’s Manual
11-128
Serial Port 4 MCP / SSP
11-169
11.12.12.1Transmit Fifo Not Full Flag TNF
Register Summary MHz Oscillator Specifications
KHz Oscillator Specifications
Internal Test
Figures
Tables
SA-1100 Power and Clock Supply Sources and States
14-4
Page
Intel StrongARM SA-1100 Microprocessor
Introduction
LCD
DMA
Features of the SA-1100 CPU for CA and DA Parts
Features of the SA-1100 CPU for AA and EA Parts
Changes to the SA-1100 Core from the SA-110
Additional Features Built into SA-1100 Chipset
Overview
SA-1100 Example System
Example System
ARM Architecture
Read Buffer
Write Buffer
Page
Functional Description
Block Diagram
SA-1100 Block Diagram
Inputs/Outputs
Signal Description
Signal Descriptions Sheet 1
Name Type Description
Signal Descriptions Sheet 2
TDO OCZ
Signal Descriptions Sheet 3
VDD
VSS
Memory Map
Pcmcia Interface Mbyte Static Memory ROM, Flash, Sram
1GB
ARM Implementation Options
Big and Little Endian
Exceptions
ROM Size Select
Power-Up Reset
Abort
Vector Summary
Address Exception Mode on Entry
Exception Priorities
Vector Summary
Coprocessors
Interrupt Latencies and Enable Timing
Page
Instruction Set
Instruction Group Result Delay Issue Cycles
Instruction Set
Instruction Timings
Page
Internal Coprocessor Instructions
Coprocessors
Register 0 ID
Coprocessor 15 Definition
Cache and MMU Control Registers Coprocessor
Register Register Reads Register Writes
Register 1 Control
Register 5 Fault Status
Register 3 Domain Access Control
Register 6 Fault Address
Register 2 Translation Table Base
Register 8 TLB Operations
Register 7 Cache Control Operations
Function
OPC2
Registers 10 12 Reserved
Register 9 Read-Buffer Operations
Access process ID register 0b000 0b0000
Register 13 Process ID Virtual Address Mapping
CRm
Dbcr Bit Action
Register 14 Debug Support Breakpoints
0b010 0b0100 Wait for interrupt 0b1000
Register 15 Test, Clock, and Idle Control
Page
Instruction Cache Icache
Caches, Write Buffer, and Read Buffer
Icache Operation
Icache Validity
Data Caches Dcaches
Icache Enable/Disable and Reset
Enabling the Icache
Disabling the Icache
Bufferable Bit B
Cacheable Bit C
Cacheable Reads C =
Noncacheable Reads C =
Dcaches Enable/Disable and Reset
Software Dcache Flush
Doubly Mapped Space
Write Buffer WB
Bufferable Bit
Write Buffer Operation
Enabling the Write Buffer
Read Buffer RB
Writes to a Bufferable and Noncacheable Location B=1,C=0
Unbufferable Writes B=0
Caches, Write Buffer, and Read Buffer
Page
Memory-Management Unit MMU
MMU Faults and CPU Aborts
Data Aborts
MMU Registers
Cacheable Reads Linefetches
Interaction of the MMU, Icache, Dcache, and Write Buffer
Buffered Writes
Valid MMU, Dcache, and Write Buffer Combinations
Mini Data Cache
To disable the MMU
Page
SA-1100 Crystal Oscillators
Clocks
RTC
ARM
Restrictions on Changing the Core Clock Configuration
Core Clock Configuration Register
Core Clock Configurations
CCF40 Core Clock Frequency in MHz MHz Crystal Oscillator
Driving SA-1100 Crystal Pins from an External Source
Clocking During Test
General-Purpose I/O
System Control Module
Gpio Pin Edge Detect
Gpio Register Definitions
Bit Name Description
Gpio Pin-Level Register Gplr
Gpio Pin Direction Register Gpdr
Bit Reset
PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0
Bit Name Description Gpio Rising-Edge Detect Register Grer
Bit Name Description Gpio Falling-Edge Detect Register Grer
31..28 Reserved
Gpio Edge Detect Status Register Gedr
Gpio Alternate Function Register Gafr
Gpio Alternate Functions
Pin Alternate Function Direction Unit Signal Description
Address Name Description
Gpio Register Locations
Interrupt Controller Register Definitions
Interrupt Controller
Interrupt Bits
Interrupt
Interrupt Controller Pending Register Icpr
Bit Position Unit Source Module
Bit Field Description
IP9 IP8 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0
Interrupt Controller Mask Register Icmr
IMn Interrupt mask n where n = 0 through
Bit Name
Interrupt Controller Level Register Iclr
Idle mode. This bit is cleared during all resets
Disable idle mask
Interrupt Controller Control Register Iccr
DIM
Real-Time Clock
Interrupt Controller Register Locations
RTC Counter Register Rcnr
RTC Status Register Rtsr
RTC Alarm Register Rtar
ALE
HZE
Trim Procedure
RTC Trim Register Rttr
Oscillator Frequency Calibration
Trim Example #1 Measured Value Has No Fractional Component
Rttr Value Calculations
Real-Time Clock Register Locations
Operating System Timer
OS Timer Match Registers 0-3 OSMR0, OSMR1, OSMR2, OSMR3
OS Timer Count Register Oscr
OS Timer Watchdog Match Enable Register Ower
WME
OS Timer Status Register Ossr
OS Timer Interrupt Enable Register Oier
Watchdog Timer
Interrupt enable channel
OS Timer Register Locations
OS Timer Register Locations
Run Mode
Power Manager
Idle Mode
Entering Idle Mode
Exiting Idle Mode
Sleep Mode
CPU Preparation for Sleep Mode
Events Causing Entry into Sleep Mode
During Sleep Mode
Sleep Shutdown Sequence
Sleep Wake-Up Sequence
Booting After Sleep Mode
Reviving the DRAMs from Self-Refresh Mode
Assumed Behavior of an SA-1100 System in Sleep Mode
Hardware Reset
RUN
Idle Sleep
Pin Operation in Sleep Mode
Pin State During Step
Pin Name Type
Power Manager Control Register Pmcr
Power Manager Registers
Opde
Power Manager General Configuration Register Pcfr
Power Manager PLL Configuration Register Ppcr
WEn
Power Manager Wake-Up Enable Register Pwer
Power Manager Sleep Status Register Pssr
BFS
VFS
Dram control hold
Bit is cleared. This bit is cleared on hardware reset
Peripheral control hold
31..5 Reserved
Power Manager Gpio Sleep State Register Pgsr
Power Manager Scratch Pad Register Pspr
Power Manager Register Locations
Power Manager Oscillator Status Register Posr
Power Manager Register Locations
Hardware reset
Reset Controller
Reset Controller Software Reset Register Rsrr
Reset Controller Registers
Software reset
SWR
Reset Controller Register Locations
Reset Controller Status Register Rcsr
Reset Controller Register Locations
Page
Overview of Operation
Memory and Pcmcia Control Module
Intel
SA-1100 Memory Controller Interface
10-2
Memory and Pcmcia Control Module
Example Memory System
Example Memory Configuration
Reads
Types of Memory Accesses
Writes
Transaction Summary
Aborts and Nonexistent Memory
Read-Lock-Write
SA-1100 Transactions
Bus Operation
Memory Configuration Registers
Physical Address Symbol Register Name
Memory Interface Control Registers
CDB2
Dram Configuration Register Mdcnfg
Cycle
31..17 DRI140 Dram refresh interval
Mem clock frequency /4
Will not be interrupted
Dram CAS Waveform Shift Registers MDCAS0, MDCAS1, MDCAS2
For Flash and SRAM, this determines the read access time
ROM or the first access of a burst ROM
Static Memory Control Registers MSC1-0
One memory clock cycle is added to this value
12..8 RDNx40 ROM delay next access
Accesses of a burst ROM
For Flash and SRAM, this determines the write pulse width
Expansion Memory Pcmcia Configuration Register Mecr
Bclk Speeds for 160-MHz Processor Core Frequency
BSxx Bit Encoding
Bclksel
Bclk Cycle Time-ns
Dram Overview
Dynamic Interface Operation
Dram Memory Size Options
Dram Row/Column Address Multiplexing
Dram Timing
Mdcnfgtrp = 4 MDCNFGCDB2 =
Addr
Dram Burst-of-Eight Transactions
Static Memory Interface
Dram Self-Refresh in Sleep Mode
Dram Refresh
10-18
ROM Interface Overview
ROM Timing Diagrams and Parameters
A42
A255
Input Data Latch
10-20
SA-1100 Developer’s Manual
Eight Beat Burst Read from Burst-of-Four ROM
Sram Timing Diagrams and Parameters
Sram Write Timing Diagram 4-Beat Burst
Sram Interface Overview
Flash Eprom Interface Overview
10-24
Flash Eprom Timing Diagrams and Parameters
Dram Access Followed by a Static Access
Static Access Followed by a Dram Access
Dram Access Followed by a Refresh Operation
General Memory BUS Timing
10-26
Pcmcia Overview
Address
10.6.1 32-Bit Data Bus Operation
10-28
External Logic for Pcmcia Implementation
12. Pcmcia External Logic for a Two-Socket Configuration
10-30
13. Pcmcia External Logic for a One-Socket Configuration
14. Pcmcia Voltage-Control Logic
Pcmcia Interface Timing Diagrams and Parameters
10-32
15. Pcmcia Memory or I/O 16-Bit Access
16. Pcmcia I/O 16-Bit Access to 8-Bit Device
Flow of Events After Reset or Exiting Sleep Mode
Initialization of the Memory Interface
10-34
Alternate Memory Bus Master Mode
Page
Read/Write Interface
Peripheral Control Module
Peripheral Register Width DMA Burst Size
Memory Organization
Peripheral Serial Protocol Base Address
Peripheral Units’ Base Addresses
LCD Controller 0h B010 Serial Port
ICP Hssp
Peripheral Units’ Interrupt Numbers
Interrupts
Interrupt
Peripheral
Peripheral Pins
Dedicated Peripheral Pins
Peripheral Gpio Pin Function
Peripheral Unit Gpio Pin Assignment
Use of the Gpio Pins for Alternate Functions
DMA Register Definitions
DMA Controller
DMA Device Address Register DDARn
D31 D0 1 0 from memory
Controller From Half-word wide
Device From To Half-word wide To From Byte-wide
Valid Settings for the DDARn Register
Ddar Fields Unit Name Function Address DA318 DS30
11-10
DMA Control/Status Register DCSRn
DMA Buffer a Transfer Count Register DBTAn
DMA Buffer a Start Address Register DBSAn
DMA Buffer B Start Address Register DBSBn
DMA Operation
DMA Buffer B Transfer Count Register DBTBn
TCB120 Transfer count buffer B
DMA Register List
Physical Address Register Name Symbol
DBTA3
DBSA3
DBSB3
DBTB3
11-16
LCD Controller
Lpclk
DMA to Memory Interface
LCD Controller Operation
Frame Buffer
11-18
PBS
Pixel bit size
13..12
To palette
Frame to palette
Encoded Pixel Data70 Bit
Unused Red Data30 Green Data30 Blue Data30
Encoded Pixel Data150
11-22
FrameBufferSize = 32 + 16 + è
Lookup Palette
Input Fifo
Output Fifo
Color/Gray-Scale Dithering
Color/Gray-Scale Intensities and Modulation Rates
Dither Value Intensity Modulation Rate
LCD Controller Register Definitions
LCD Controller Pins
LCD Controller Control Register
LCD Enable LEN
Color/Monochrome Select CMS
Single-/Dual-Panel Select SDS
Single Passive Screen Portion Pins
LCD Controller Data Pin Utilization
Dual Panel Active Panel
11-28
LCD Data-Pin Pixel Ordering
Base Address Update Interrupt Mask BAM
LCD Disable Done Interrupt Mask LDM
Error Interrupt Mask ERM
Passive/Active Display Select PAS
11-30
Double-Pixel Data DPD Pin Mode
Palette DMA Request Delay PDD
11.7.3.8 Big/Little Endian Select BLE
CMS
LEN
SDS
LDM
BLE
PAS
DPD
PDD
Horizontal Sync Pulse Width HSW
Pixels Per Line PPL
End-of-Line Pixel Clock Wait Count ELW
11-34
PPL
Beginning-of-Line Pixel Clock Wait Count BLW
HSW
ELW
Lines Per Panel LPP
Vertical Sync Pulse Width VSW
11-36
Beginning-of-Frame Line Clock Wait Count BFW
End-of-Frame Line Clock Wait Count EFW
VSW
LPP
EFW
BFW
AC Bias Pin Frequency ACB
Pixel Clock Divider PCD
Vertical Sync Polarity VSP
AC Bias Pin Transitions Per Interrupt API
Horizontal Sync Polarity HSP
Pixel Clock Polarity PCP
Address 0h B010
Output Enable Polarity OEP
HSP
LCD Controller DMA Registers
PCP
OEP
31..0
DMA Channel 1 Base Address Register
DBAR1
DMA channel 1 base address pointer
DCAR1
DMA Channel 1 Current Address Register
DMA channel 1 current address pointer
Equal to the calculated end address of the buffer
DBAR2
DMA Channel 2 Base and Current Address Registers
DCAR2
DMA channel 2 current address pointer
Base Address Update Flag BAU read-only, maskable interrupt
LCD Disable Done Flag LDD read/write, maskable interrupt
Bus Error Status BER read/write, maskable interrupt
LCD Controller Status Register
AC Bias Count Status ABC read/write, nonmaskable interrupt
BAU
LDD
ABC
BER
IOL
IUL
LCD Controller Control, DMA, and Status Register Locations
LCD Controller Register Locations
LDDx0
LCD Controller Pin Timing Diagrams
Lfclk Llclk Lpclk
LDDx0
11-52
DPD =
12. Passive Mode Pixel Clock and Data Pin Timing
11-54
13. Active Mode Timing
14. Active Mode Pixel Clock and Data Pin Timing
Serial Port 0 USB Device Controller
USB Operation
11-56
10. USB Bus States
Signalling Levels
Bus State UDC+/UDC- Pin Levels
Port
Bit Encoding
Bit Value Digital Data Nrzi Data
11-58
11. Endpoint Field Addressing
Field Formats
Endpoint Field Value UDC Endpoint Selected
Endpoint
PID
Packet Formats
CRC5
CRC16
Action
Transaction Formats
OUT
Packets from UDC to host are boldface
UDC Device Requests
Setup DATA0
Action Token Packet Data Packet
11-62
UDC Register Definitions
12. Host Device Request Summary
Request Name
UDC Control Register
Suspend/Resume Interrupt Mask SRM
Reset Interrupt Mask REM
Address 0h 8000
Udccr
UDC OUT Max Packet Register
UDC Address Register
Udcar
Udcomp
UDC in Max Packet Register
Address 0h 8000 000C
Udcimp
UDC Endpoint 0 Control/Status Register
UDCCS0
Serviced Setup End SSE
SSE FST SST IPR OPR
SSE
Receive Packet Error RPE
Receive Fifo Service RFS
UDC Endpoint 1 Control/Status Register
Receive Packet Complete RPC
UDCCS1
Bits 7..6 Reserved
RNE FST SST RPE RPC RFS
RNE
Transmit Packet Error TPE
Transmit Fifo Service TFS
UDC Endpoint 2 Control/Status Register
Transmit Packet Complete TPC
FST SST TUR TPE TPC TFS
UDCCS2
UDC Endpoint 0 Write Count Register
UDC Endpoint 0 Data Register
UDCD0
Data
Uddr
UDC Data Register
Top/bottom of transmit/receive Fifo data
Read Bottom of receive Fifo data
UDC Status/Interrupt Register
Udcsr
Reset Interrupt Request Rstir
Rstir Resir Susir TIR RIR EIR
Rstir
Serial Port 1 SDLC/UART
UDC Register Locations
13. UDC Control, Data, and Status Register Locations
Sdlc Operation
Address Field
Frame Format
Control Field
CRC-CCITT
Data Field
CRC Field
Baud Rate Generation
11-82
Receive Operation
Simultaneous Use of the Uart and Sdlc
Transmit Operation
Sdlc Register Definitions
CPU and DMA Register Access Sizes
Transmit and Receive FIFOs
11-84
Sdlc Control Register
Loopback Mode LBM
SDLC/UART Select SUS
Single/Double Flag Select SDF
Bit Modulation Select BMS
Sample Clock Enable SCE
Sample Clock Direction SCD
11-86
Transmit Clock Edge Select TCE
Receive Clock Edge Select RCE
Address 0h 8002
SDCR0
TCE
Abort After Frame AAF
Receive Enable RXE
Transmit Enable TXE
Receive Fifo Interrupt Enable RIE
Transmit Fifo Interrupt Enable TIE
Receiver Abort Interrupt EnableRAE
Address Match Enable AME
Transmit Fifo Underrun Select TUS
11-90
Read/Write
SDCR1
RAE TUS AME TIE RIE RXE TXE AAF
RAE
Address Match Value AMV
SDCR2
AMV
Baud Rate Divisor BRD
Sdlc Control Registers 3
Address 0h 8002 006C
SDCR3
11-94
Sdlc Data Register
Sddr
Address 0h 0078
ROR CRE EOF
ROR
Transmit Underrun Status TUR read/write, maskable interrupt
Sdlc Status Register
Receiver Abort Status RAB read/write, maskable interrupt
11-96
SA-1100 Developer’s Manual 11-97
RFS TFS RAB TUR EIF
SDSR0
Transmitter Busy Flag TBY read-only, noninterruptible
Receiver Synchronized Flag RSY read-only, noninterruptible
Receive Fifo Not Empty Flag RNE read-only, noninterruptible
Transmit Fifo Not Full Flag TNF read-only, noninterruptible
CRC Error Status CRE read-only, noninterruptible
Receiver Overrun Status ROR read-only, noninterruptible
11-100
ROR CRE EOF RTD TNF RNE
SDSR1
RSY
TBY
14. Uart Control, Data, and Status Register Locations
Uart Register Locations
Serial Port 2 Infrared Communications Port ICP
Sdlc Register Locations
15. Sdlc Control, Data, and Status Register Locations
HP-SIR*Modulation
Low-Speed ICP Operation
Uart Frame Format
11-104
High-Speed ICP Operation
11.10.2.1 4PPM Modulation
Chip Timeslots Data =
Hssp Frame Format
SA-1100 Developer’s Manual 11-107
11-108
SA-1100 Developer’s Manual 11-109
11-110
Low-Power Mode LPM
HP-SIR Enable HSE
Uart Register Definition
Uart Control Register
Hssp Control Register
Hssp Register Definitions
IrDA Transmission Rate ITR
LPM
SA-1100 Developer’s Manual 11-113
11-114
Address 0h 8004
HSCR0
AME TIM RIM RXE TXE TUS LBM ITR
HSCR1
Search for the next preamble
11-116
Receive Pin Polarity Select RXP
Transmit Pin Polarity Select TXP
HSCR2
0h 9006
RXP TXP
RXP
Hssp Data Register
Hsdr
Address 0h 8004 006C
Last Fifo entry is transferred to the ROR bit
HSSR1
Receiver Abort Status RAB read/write, nonmaskable interrupt
Hssp Status Register
11-122
HSSR0
Framing Error Status FRE read/write, nonmaskable interrupt
FRE RFS TFS RAB TUR EIF
FRE
11-124
End-of-Frame Flag EOF read-only, noninterruptible
SA-1100 Developer’s Manual 11-125
ROR CRE EOF TNF RNE TBY RSY
HSSR1
Hssp Register Locations
16. Uart Control, Data, and Status Register Locations
17. Hssp Control, Data, and Status Register Locations
Uart Operation
Serial Port 3 Uart
LSB MSB
11-128
30. NRZ Bit Encoding Example 0100
11-130
Parity Enable PE
Uart Register Definitions
11.11.3.2 Odd/Even Parity Select OES
Stop Bit Select SBS
Data Size Select DSS
11-132
TCE RCE SCE DSS SBS OES
UTCR0
Uart Control Registers 1
Bit Reset BRD70
UTCR1
UTCR2
Receiver Enable RXE
Transmitter Enable TXE
Break BRK
LBM TIE RIE BRK TXE RXE
UTCR3
Uart Data Register
ROR FRE PRE
Utdr
Uart Status Register
Error in Fifo Flag EIF read-only, nonmaskable interrupt
Receiver Idle Status RID read/write, maskable interrupt
11-140
Address 0h 8005 001C
UTSR0
EIF REB RBB RID RFS TFS
11-142
Parity Error Flag PRE read-only, noninterruptible
Receiver Overrun Flag ROR read-only, noninterruptible
Framing Error Flag FRE read-only, noninterruptible
UTSR1
Read-Only
ROR FRE PRE TNF RNE TBY
Serial Port 4 MCP / SSP
11-146
MCP Operation
31. MCP Frame Data Format
11-148
Audio and Telecom Sample Rates and Data Transfer
MCP Transmit and Receive Fifo Operation
Codec Control Register Data Transfer
Bit Audio Data Telecom Data
11-150
Alternate SSP Pin Assignment
External Clock Operation
MCP Control Register
MCP Register Definitions
Audio Sample Rate Divisor ASD
11-152
Telecom Sample Rate Divisor TSD
11.12.3.5 A/D Sampling Mode ADM
Multimedia Communications Port Enable MCE
External Clock Select ECS
11-154
Telecom Receive Fifo Interrupt Enable TRE
Telecom Transmit Fifo Interrupt Enable TTE
Audio Transmit Fifo Interrupt Enable ATE
Audio Receive Fifo Interrupt Enable are
ASD
External Clock Prescaler ECP
Audio sample rate divisor
TSD
ECS
MCE
ADM
TTE
MCP Data Registers
Clock Frequency Select CFS
CFS
Address 0h 8006 MCP Data Register 0 MCDR0 Read/Write
MCP Data Register
Reserved for future enhancements
15..4
Address 0h 8006 000C MCP Data Register 1 MCDR1 Read/Write
SA-1100 Developer’s Manual 11-161
Address 0h 8006 MCP Data Register 2 MCDR2 Read/Write
Reg Address R/W Reset Bit
15..0 Codec
Register read Read/write Read Returns a zero
MCP Status Register
11-164
SA-1100 Developer’s Manual 11-165
Telecom Codec Enabled Flag TCE read-only, noninterruptible
Audio Codec Enabled Flag ACE read-only, noninterruptible
Codec Write Completed Flag CWC read-only, noninterruptible
Codec Read Completed Flag CRC read-only, noninterruptible
ARS
ATS
TTS
TRS
TRO
TTU
ANF
ANE
SSP Operation
11-170
35. Texas Instruments* Synchronous Serial Frame Format
36. Motorola* SPI Frame Format
11-172
37. National Microwire* Frame Format
Bit Bit Data
SSP Transmit and Receive FIFOs
SSP Register Definitions
SSP Control Register
11-174
Frame Format FRF
Synchronous Serial Port Enable SSE
Serial Clock Rate SCR
FRF
SCR
Serial Clock Polarity SPO
Sclk SPO=0 Sclk SPO=1 Sfrm TXD4 RXD4
Serial Clock Phase SPH
LSB
11-178
SPO
SSP Data Register
Address 0h 8007 006C
Justifies data and zero fills unused bits 11-180
SSP Busy Flag BSY read-only, noninterruptible
SSP Status Register
BSY
SSP Register Locations
MCP Register Locations
19. MCP Control, Data, and Status Register Locations
20. SSP Control, Data, and Status Register Locations
Peripheral Pin Controller PPC
PPC Operation
11-184
PPC Pin Direction Register
PPC Register Definitions
Sclk
Address 0h 9006 Ppsr PPC Pin StateRegister Read/Write
PPC Pin State Register
Read Current state of LCD pixel clock pin returned
LCD pixel clock pin state
LCD line clock pin state
Read Current state of LCD line clock pin returned
Uart Pin Reassignment UPR
PPC Pin Assignment Register
SSP Pin Reassignment SPR
UPR
11-190
PPC Sleep Mode Pin Direction Register
LCD pixel clock pin configured as input during sleep
LCD pixel clock sleep mode pin direction
LCD line clock sleep mode pin direction
LCD line clock pin configured as input during sleep
PPC Pin Flag Register
21. PPC Control and Flag Register Locations
PPC Register Locations
Page
DC Parameters
Symbol Parameter Min Max Units
Absolute Maximum Ratings
SA-1100 DC Maximum Ratings
DC Operating Conditions
Symbol Parameter Min Nom Max Units
SA-1100 DC Operating Conditions
× Vddx
Parameter SA-1100 Units
Power Supply Voltages and Currents
VDD
Vddx
Page
AC Parameters
Test Conditions
SA-1100 Output Derating
Module Considerations
Memory Bus and Pcmcia Signal Timings
Memory Bus Memory Bus Out
13-2
LCD Controller Signals
MCP Signals
LLDD70 fall
Timing Parameters
Pin Name Symbol Parameter Min Max Unit
SA-1100 AC Timing Table for AA and BA Parts
Sfrmc
Asynchronous Signal Timing Descriptions
Page
Mechanical Data and Packaging Information
Package and Pinout
14-2
SA-1100 Pinout 208-Pin Quad Flat Pack
SA-1100 256 Mini-Ball Grid Array Mechanical Drawing
Mini-Ball Grid Array mBGA
14-4
SA-1100 Pinout 256-Pin Mini-Ball Grid Array
Debug Support
Instruction Breakpoint
Data Breakpoint
Page
Boundary-Scan Test Interface
Test Access Port TAP Controller State Transitions
Pull-Up Resistors
Reset
Instruction Register
Public Instructions
Extest
SAMPLE/PRELOAD
Clamp
Idcode
Highz
Bypass
16-4
Bypass Register
Test Data Registers
16.6.2 SA-1100 Device Identification ID Code Register
16.6.3 SA-1100 Boundary-Scan BS Register
16-6
Tbscl Tbsch
Boundary-Scan Interface Signals
Tbsis Tbsih
Tbsoh Tbsod Data Tbsss Tbssh Data Out Tbsdh Tbsdd
Data Out Tbsde
Tbsoe
Tbsr
Tbsrs Tbsrh
SA-1100 Boundary-Scan Interface Timing
Symbol Parameter Minimum Typical Maximum Units
Page
Register Summary
Tucr
DMA control/status register 2 write ones to set
B000 0044
B000 0048 Write ones to clear 004C Read only 0050
B000 0054
Ucdomp
8031
Sdlc Registers Serial Port 8002
8003 Reserved 8003 001C
8004 007C 0h 8004 Ffff Reserved
Uart Registers Serial Port 8005
8007 0078 0h 8007 Ffff Reserved PPC Registers 9006
9006 0034 0h 9006 Ffff Reserved
MHz Oscillator Specifications B
Specifications
System Specifications
Specification Minimum Typical Maximum Unit
MHz Oscillator Specifications
Quartz Crystal Specification
Specification
Typical Maximum Unit
Page
Temperature Range
KHz Oscillator Specifications C
Current Consumption
Startup Time
Parasitic Capacitance Off-chip Between Txtal and Textal
Frequency Shift Due to Temperature Effect on the Circuit
Parasitic Resistance Between Txtal and Textal
Parasitic Resistance Between Txtal or Textal and VSS
Therefore, the values for Q
Other providers supply a Quality Factor, Q, instead of Rm
Corresponding to specified range of Rm are supplied
Following table
KHz Oscillator Specifications
Internal Test
Test Unit Control Register Tucr
PMD
TSEL2 TSEL1 TSEL0
TSEL2-0
Page
Support, Products, and Documentation
