Intel SA-1100 manual CRC Error Status CRE read-only, noninterruptible, 11-100

Peripheral Control Module

register. After the error in FIFO (EIF) status bit is set, the user should always read SDSR1 first to check EOF before reading the data value from SDDR because EOF corresponds to the current data byte at the bottom of the receive FIFO and is updated each time data is removed from the FIFO.

11.9.9.7CRC Error Status (CRE) (read-only, noninterruptible)

The CRC error flag (CRE) is set when the CRC value calculated by the receive logic does not match the CRC value contained within the incoming serial data stream.

The receive FIFO contains 3 tag bits (8, 9, and 10) that are not directly readable. Whenever a CRC error is detected, the 9th bit is set within the top entry of the receive FIFO, corresponding to the last byte of data within the frame. This tag travels along with the last piece of data from the frame as it moves down the FIFO. Each time a data value is transferred to the bottom of the FIFO (caused by a read of the previous value), the state of the tag bit is moved from the FIFO to the CRE bit in the status register, indicating whether or not the frame has encountered a CRC error. After the error in the FIFO (EIF) status bit is set, the user should always read SDSR1 first to check CRE before reading the data value from SDDR because CRE corresponds to the current data byte at the bottom of the receive FIFO and is updated each time data is removed from the FIFO.

11.9.9.8Receiver Overrun Status (ROR) (read-only, noninterruptible)

The receiver overrun flag (ROR) is set when the receive logic attempts to place data into the receive FIFO after it has been completely filled.

The receive FIFO contains 3 tag bits (8, 9, and 10) that are not directly readable. The 10th bit is set within the top entry of the receive FIFO whenever an overrun occurs. This tag travels along with the last “good” data value before the overflow occurred as it moves down the FIFO. Each time a data value is transferred to the bottom of the FIFO (caused by a read of the previous value), the state of the tag bit is moved from the FIFO to the ROR bit in the status register, indicating that the next value in the FIFO is the last “good” piece of data before the overflow occurred. After the error in the FIFO (EIF) status bit is set, the user should always read SDSR1 first to check CRE before reading the data value from SDDR because CRE corresponds to the current data byte at the bottom of the receive FIFO and is updated each time data is removed from the FIFO.

11-100 SA-1100 Developer’s Manual